From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C91AD81911 for ; Mon, 26 Dec 2016 03:21:11 -0800 (PST) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP; 26 Dec 2016 03:21:11 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,404,1477983600"; d="scan'208";a="916215829" Received: from jfan12-desk.ccr.corp.intel.com ([10.239.9.5]) by orsmga003.jf.intel.com with ESMTP; 26 Dec 2016 03:21:10 -0800 From: Jeff Fan To: edk2-devel@lists.01.org Cc: Feng Tian , Kinney, Michael D , Ruiyu Ni Date: Mon, 26 Dec 2016 19:21:00 +0800 Message-Id: <20161226112102.25512-5-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20161226112102.25512-1-jeff.fan@intel.com> References: <20161226112102.25512-1-jeff.fan@intel.com> Subject: [PATCH 4/6] UefiCpuPkg/MpInitLib: Swap local APIC timer interrupt state X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 26 Dec 2016 11:21:11 -0000 We need to swap local APIC timer interrupt state between old BSP and new BSP. Cc: Feng Tian Cc: Kinney, Michael D Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Library/MpInitLib/MpLib.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpInitLib/MpLib.c index 9dae827..77d855a 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1512,8 +1512,14 @@ SwitchBSPWorker ( CPU_STATE State; MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr; BOOLEAN OldInterruptState; + BOOLEAN OldTimerInterruptState; // + // Save and Disable Local APIC timer interrupt + // + OldTimerInterruptState = GetApicTimerInterruptState (); + DisableApicTimerInterrupt (); + // // Before send both BSP and AP to a procedure to exchange their roles, // interrupt must be disabled. This is because during the exchange role // process, 2 CPU may use 1 stack. If interrupt happens, the stack will @@ -1613,6 +1619,9 @@ SwitchBSPWorker ( // SetInterruptState (OldInterruptState); + if (OldTimerInterruptState) { + EnableApicTimerInterrupt (); + } return EFI_SUCCESS; } -- 2.9.3.windows.2