From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7F6D081A03 for ; Fri, 6 Jan 2017 09:28:53 -0800 (PST) Received: from int-mx10.intmail.prod.int.phx2.redhat.com (int-mx10.intmail.prod.int.phx2.redhat.com [10.5.11.23]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E0CF6285C1; Fri, 6 Jan 2017 17:28:53 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-54.phx2.redhat.com [10.3.116.54]) by int-mx10.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id v06HSqAn010783; Fri, 6 Jan 2017 12:28:52 -0500 From: Laszlo Ersek To: edk2-devel-01 Cc: Jiewen Yao , Jordan Justen Date: Fri, 6 Jan 2017 18:28:47 +0100 Message-Id: <20170106172847.943-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.23 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.30]); Fri, 06 Jan 2017 17:28:53 +0000 (UTC) Subject: [PATCH v2] OvmfPkg/SmmControl2Dxe: correct PCI_CONFIG_READ_WRITE in S3 boot script X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 06 Jan 2017 17:28:53 -0000 EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE expects the PCI address to access in UEFI encoding, not in edk2/PciLib encoding. Introduce the POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() macro, and with it, store the ICH9_GEN_PMCON_1 register's address to the boot script in UEFI representation. Cc: Jiewen Yao Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- Notes: v2: - replace ConvertPciLibToEfiPciAddress() with POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS() [Jordan, Jiewen] OvmfPkg/Include/IndustryStandard/Q35MchIch9.h | 6 ++++++ OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c | 5 ++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h index 4dc2c39901c1..f480455ae432 100644 --- a/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h +++ b/OvmfPkg/Include/IndustryStandard/Q35MchIch9.h @@ -19,6 +19,9 @@ #define __Q35_MCH_ICH9_H__ #include +#include +#include +#include // // Host Bridge Device ID (DID) value for Q35/MCH @@ -75,6 +78,9 @@ #define POWER_MGMT_REGISTER_Q35(Offset) \ PCI_LIB_ADDRESS (0, 0x1f, 0, (Offset)) +#define POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS(Offset) \ + EFI_PCI_ADDRESS (0, 0x1f, 0, (Offset)) + #define ICH9_PMBASE 0x40 #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \ BIT10 | BIT9 | BIT8 | BIT7) diff --git a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c index 82549b0a7e35..6c03e17a3a8d 100644 --- a/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c +++ b/OvmfPkg/SmmControl2Dxe/SmmControl2Dxe.c @@ -311,6 +311,7 @@ OnS3SaveStateInstalled ( EFI_STATUS Status; EFI_S3_SAVE_STATE_PROTOCOL *S3SaveState; UINT32 SmiEnOrMask, SmiEnAndMask; + UINT64 GenPmCon1Address; UINT16 GenPmCon1OrMask, GenPmCon1AndMask; ASSERT (Event == mS3SaveStateInstalled); @@ -342,13 +343,15 @@ OnS3SaveStateInstalled ( CpuDeadLoop (); } + GenPmCon1Address = POWER_MGMT_REGISTER_Q35_EFI_PCI_ADDRESS ( + ICH9_GEN_PMCON_1); GenPmCon1OrMask = ICH9_GEN_PMCON_1_SMI_LOCK; GenPmCon1AndMask = MAX_UINT16; Status = S3SaveState->Write ( S3SaveState, EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE, EfiBootScriptWidthUint16, - (UINT64)POWER_MGMT_REGISTER_Q35 (ICH9_GEN_PMCON_1), + GenPmCon1Address, &GenPmCon1OrMask, &GenPmCon1AndMask ); -- 2.9.3