From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x236.google.com (mail-wm0-x236.google.com [IPv6:2a00:1450:400c:c09::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7636981E44 for ; Wed, 18 Jan 2017 14:05:05 -0800 (PST) Received: by mail-wm0-x236.google.com with SMTP id c85so263797252wmi.1 for ; Wed, 18 Jan 2017 14:05:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=eoWv6sTTtpIsqCTfUB5NELu9CESRv4LYzu21n5CCjKg=; b=DbYadYxWdirCOghRBdfQEvcYkPnpIKeSRMahVcw6QWngqHmmRq4aScYb++T7lN6QSp G8dgMBU2VZn6k1WTJLt6dcCvuVHpxwwrtHDCGJGDyfeejy5308u+Wy9/VlWq+fFUAkTe LSgzjJ6lbcQLJAl8LvCFrA62xQUe3txOBRViw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=eoWv6sTTtpIsqCTfUB5NELu9CESRv4LYzu21n5CCjKg=; b=cdEbvICf+z+hMNF2I3g9AxP46rGo1qte53dTx+2IXdGTbNKcPUl5i+rPLRQ8Bvnh7G vALZW58jkEUTnm/PO33lnfK8PV2b1Ayxo1iYKkS14nMI8liCwPRnmyWrfBiLb/o6HZc7 wkndgDEdU6iFUT9FMiYFaFfjYd+HDjA21mnsEZX42dFM5WjMm5vMb+FQAYgeSq/RRDRp XG/MSWGw15PYj+8np5vb9o3kehIrx5vq5gmbaZDL7Z7FmB44rRmKttpSQrf7tehJRwOh 8cxOE/rp5qqLfMX0wRJ2mx6RZWsCpRRADW0jEdbeZ1wBdzgNE+52kIzfFw6vim/aA7q+ BlMg== X-Gm-Message-State: AIkVDXIbd5Jz6vwoaglSuxvXOu91+cUPe0DfwHC58pAixJKSkDYR/mSdEfTR35nq8exLZ2Jl X-Received: by 10.223.141.133 with SMTP id o5mr5319541wrb.100.1484777103490; Wed, 18 Jan 2017 14:05:03 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m78sm7795705wmd.8.2017.01.18.14.05.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 18 Jan 2017 14:05:02 -0800 (PST) Date: Wed, 18 Jan 2017 22:05:00 +0000 From: Leif Lindholm To: achin.gupta@arm.com Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nd@arm.com Message-ID: <20170118220500.GW25883@bivouac.eciton.net> References: <1484771046-21296-1-git-send-email-achin.gupta@arm.com> MIME-Version: 1.0 In-Reply-To: <1484771046-21296-1-git-send-email-achin.gupta@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH] ArmPlatformPkg/ArmVExpressPkg: Fix memory attributes for NOR Flash X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Jan 2017 22:05:05 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Achin, On Wed, Jan 18, 2017 at 08:24:06PM +0000, achin.gupta@arm.com wrote: > From: Achin Gupta > > The NOR flash banks were being mapped in the translation tables with the same > memory attributes as RAM in the system. These attributes mark the region as > Normal Memory and could additionally be cacheable or non-cacheable. > > Either type of attributes are unsuitable for NOR Flash since write operations > could be performed on it. Normal Memory does not guarantee ordering of > transactions that Device memory does. So the commands sent to the Flash device > may not arrive in the right order unless barriers are used. Commands might not > get past the CPU caches in case the region has been mapped with cacheable > attributes. > > This patch fixes the problem by mapping the NOR Flash memory region with Device > memory attributes. To add some background to Ard's comment - this was not unintentionally done: https://github.com/tianocore/edk2/commit/19bb46c411279dcd30d540c56e5993c5f771c319 Was the reasoning behind this commit incorrect - do you have a (pre-DXE?) use-case that creates a problem? Regards, Leif > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Achin Gupta > --- > ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > index 14c7e8e..2685114 100644 > --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > @@ -116,7 +116,7 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; > VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; > VirtualMemoryTable[Index].Length = ARM_VE_SMB_NOR0_SZ + ARM_VE_SMB_NOR1_SZ; > - VirtualMemoryTable[Index].Attributes = CacheAttributes; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > // SMB CS2 - SRAM > VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE; > -- > 1.9.1 >