From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4196F81FAD for ; Thu, 26 Jan 2017 04:11:09 -0800 (PST) Received: by mail-wm0-x22a.google.com with SMTP id c206so80681798wme.0 for ; Thu, 26 Jan 2017 04:11:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=2SiZPMkjhf8T11oOOiJVjZm49UkMSGIoalZaQ9shH/0=; b=DG6tChVeS46exiq07/u44N8dngyl84AdDIdd/Xg9QkPMY7Vx8I6BGmyXf0E3YQLrE3 aIfxrmEQG8l2ieOP8VT8y45GbimZtSJXF6LL8zeK3KXyoHYZtCuuGfjp7cj8W5WXyUEu 3eNP/cuEjkzTeBqtYZHbACHl0pLfVcjPYoIc0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=2SiZPMkjhf8T11oOOiJVjZm49UkMSGIoalZaQ9shH/0=; b=mPyoXuMHdcUEmNe+UYUZPBnMNgLWSUGgajerx0vwUmF41sTw9vGbmhfTFIy7jPD54/ aJYx1AwmAAFLnPkR6GUVtwkg1LrkuqYMsv/P/BR0nD1xlhMy6SFHMDPvFGIyMF+INdmu 3sf/jvrOrE7U9VILbm0+yH8hlMFbwzYizKwYgVP6Mwcli2GOPhvrCrUOubMYo3L+oBmc wMdrBI9+YogQsXQ+prJVXa4ba6aoxk1YSj/FlRLSEc1NC5wisvlMg96T85wSpwfVUTPE Hgwm0BSEsztZ6w+8jjSk8eaCftzjB/Gea9zCHwYK5gAy56KWF6ugDwJFrpeibDRAEts9 nd0w== X-Gm-Message-State: AIkVDXING9enPV1FDBSwonptTuahdaYM1JutvbxLxc8dnQ5gSvbl2f3SdG2I37o/iLl9OKHd X-Received: by 10.223.146.196 with SMTP id 62mr2226650wrn.199.1485432667841; Thu, 26 Jan 2017 04:11:07 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id e72sm13953081wma.16.2017.01.26.04.11.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 26 Jan 2017 04:11:07 -0800 (PST) Date: Thu, 26 Jan 2017 12:11:05 +0000 From: Leif Lindholm To: Jiewen Yao Cc: edk2-devel@lists.01.org, Ard Biesheuvel , Andrew Fish Message-ID: <20170126121105.GW25883@bivouac.eciton.net> References: <1485419955-26652-1-git-send-email-jiewen.yao@intel.com> <1485419955-26652-3-git-send-email-jiewen.yao@intel.com> MIME-Version: 1.0 In-Reply-To: <1485419955-26652-3-git-send-email-jiewen.yao@intel.com> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH 2/3] ArmPkg/CpuDxe: Correct EFI_MEMORY_RO usage X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jan 2017 12:11:09 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jan 26, 2017 at 04:39:14PM +0800, Jiewen Yao wrote: > Current Arm CpuDxe driver uses EFI_MEMORY_WP for write protection, > according to UEFI spec, we should use EFI_MEMORY_RO for write protection. > The EFI_MEMORY_WP is the cache attribute instead of memory attribute. Hi Jiewen, The change looks sane, given the clarification of the specification, but there are several instances of EFI_MEMORY_WP in comments left around from Andrew Fish's original ARM implementation. I think they should be updated too. Andrew: can you confirm what the below snipped from ArmPkg/Drivers/CpuDxe/Arm/Mmu.c was meant to convey? --- case TT_DESCRIPTOR_SECTION_AP_NO_NO: // no read, no write //*GcdAttributes |= EFI_MEMORY_WP | EFI_MEMORY_RP; --- Regards, Leif > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jiewen Yao > --- > ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 2 +- > ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 5 +---- > 2 files changed, 2 insertions(+), 5 deletions(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > index d8bb419..4703b33 100644 > --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > @@ -224,7 +224,7 @@ EfiAttributeToArmAttribute ( > ArmAttributes |= TT_AF; > > // Determine protection attributes > - if (EfiAttributes & EFI_MEMORY_WP) { > + if (EfiAttributes & EFI_MEMORY_RO) { > ArmAttributes |= TT_AP_RO_RO; > } > > diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > index 14fc22d..e375cbe 100644 > --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > @@ -730,9 +730,6 @@ EfiAttributeToArmAttribute ( > ArmAttributes = TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 > break; > > - case EFI_MEMORY_WP: > - case EFI_MEMORY_XP: > - case EFI_MEMORY_RP: > case EFI_MEMORY_UCE: > default: > // Cannot be implemented UEFI definition unclear for ARM > @@ -743,7 +740,7 @@ EfiAttributeToArmAttribute ( > } > > // Determine protection attributes > - if (EfiAttributes & EFI_MEMORY_WP) { > + if (EfiAttributes & EFI_MEMORY_RO) { > ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RO_RO; > } else { > ArmAttributes |= TT_DESCRIPTOR_SECTION_AP_RW_RW; > -- > 2.7.4.windows.1 >