From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22b.google.com (mail-wr0-x22b.google.com [IPv6:2a00:1450:400c:c0c::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B9A4A82035 for ; Fri, 10 Feb 2017 09:54:09 -0800 (PST) Received: by mail-wr0-x22b.google.com with SMTP id k90so113237796wrc.3 for ; Fri, 10 Feb 2017 09:54:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ESzo83QyEdVarbS5BdiruIZlHkF29wsvr5oVl/ebvVY=; b=AfYSGWLrny+tMw52p99z5r/AVXyqNRjWDJ/uZ6L0XuRD8R4mDixhrMFur5dMRjZluS cWqCXnakoiZZcPPUbciN+es4G89KTREhENr49ewRIiQM42XFX7SYmqWqOYL2hK+uvCec UAw69pfpJqtM1ffpK4n+Li5IFQA0CW9uXrDRc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ESzo83QyEdVarbS5BdiruIZlHkF29wsvr5oVl/ebvVY=; b=FGTUo3qcPLRoWYlbDZyLGzDL16192qpq7iky7J014RVlcn7mM+Tlc77CHdizCpnlvt O2+nVh98CEkGwmixim3UnFTeCCm4rCp9y++2IWdMiPEC/97rFSQVbL43kQUN1yMJyJwv E7Kp6KXHf+Oh2x0jK84GwDYPwbbxUVQEyHmcs97GcG+B87jeL3xyEWqdHcsuata5bCkd uCbMxlX2SsNFfzhwuaA6RNHs4iXcAVa1HhZdxlajj8MULuVpCRMX0ObOX2cQ0KP8L2zb 5sHlOk+TYKRwVhILZDjRJUdAoWbWky/iV/F2iTLcx+fOWmEHfNScXBZ2XVjpRiZz5z0Q EqfQ== X-Gm-Message-State: AMke39lHwOWS77+GTw/mgzDHB01HU2PTA8wbzwrTeiXLJuurYM9Gwfdst0/5xxv1kLPBP6GC X-Received: by 10.223.160.206 with SMTP id n14mr8907204wrn.31.1486749248158; Fri, 10 Feb 2017 09:54:08 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id o143sm2468598wmd.3.2017.02.10.09.54.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Feb 2017 09:54:07 -0800 (PST) Date: Fri, 10 Feb 2017 17:54:05 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, jiewen.yao@intel.com, feng.tian@intel.com, michael.d.kinney@intel.com, jeff.fan@intel.com, star.zeng@intel.com Message-ID: <20170210175405.GN16034@bivouac.eciton.net> References: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> <1486661891-7888-3-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1486661891-7888-3-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH 2/4] ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttribute X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Feb 2017 17:54:10 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Feb 09, 2017 at 05:38:09PM +0000, Ard Biesheuvel wrote: > The single user of EfiAttributeToArmAttribute () is the protocol > method EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), which uses the > return value to compare against the ARM attributes of an existing mapping, > to infer whether it is actually necessary to change anything, or whether > the requested update is redundant. This saves some cache and TLB > maintenance on 32-bit ARM systems that use uncached translation tables. > > However, EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() may be invoked with > only permission bits set, in which case the implied requested action is to > update the permissions of the region without modifying the cacheability > attributes. This is currently not possible, because > EfiAttributeToArmAttribute () ASSERT()s [on AArch64] on Attributes arguments > that lack a cacheability bit. > > So let's simply return TT_ATTR_INDX_INVALID (AArch64) or > TT_DESCRIPTOR_SECTION_TYPE_FAULT (ARM) in these cases (or'ed with the > appropriate permission bits). This way, the return value is equally > suitable for checking whether the attributes need to be modified, but > in a way that accommodates the use without a cacheability bit set. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 4 +--- > ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 3 --- > 2 files changed, 1 insertion(+), 6 deletions(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > index 15d5a8173233..7688846e70cb 100644 > --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > @@ -216,9 +216,7 @@ EfiAttributeToArmAttribute ( > ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK; > break; > default: > - DEBUG ((EFI_D_ERROR, "EfiAttributeToArmAttribute: 0x%lX attributes is not supported.\n", EfiAttributes)); > - ASSERT (0); > - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; > + ArmAttributes = TT_ATTR_INDX_MASK; Commit message says TT_ATTR_INDX_INVALID - which one is intended to be correct? / Leif > } > > // Set the access flag to match the block attributes > diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > index 6dcfba69e879..b6ba975b353a 100644 > --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > @@ -733,10 +733,7 @@ EfiAttributeToArmAttribute ( > > case EFI_MEMORY_UCE: > default: > - // Cannot be implemented UEFI definition unclear for ARM > - // Cause a page fault if these ranges are accessed. > ArmAttributes = TT_DESCRIPTOR_SECTION_TYPE_FAULT; > - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): Unsupported attribute %x will page fault on access\n", EfiAttributes)); > break; > } > > -- > 2.7.4 >