From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E523F82035 for ; Fri, 10 Feb 2017 09:59:58 -0800 (PST) Received: by mail-wr0-x235.google.com with SMTP id o16so113738793wra.1 for ; Fri, 10 Feb 2017 09:59:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0zH+4CbhYMDrO+KkuM0GN8x1fkEGP0SUjTN2LzsgHk0=; b=gGLW5KbtbE6L9fFe6596uIP2XIpf6hfViVKOjhgBccj2cSj/L/ZixYRmd/LcLfMrnJ HBQKClIH1wJqYVIcjjKrI1fYb1CgxncFiCqUBUHxSbmzgu6t2xDKUQqUuXxZASg8sgbG fifMxjIMLD0fqfu5G5CTdYZuv4qriNnKreAo8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=0zH+4CbhYMDrO+KkuM0GN8x1fkEGP0SUjTN2LzsgHk0=; b=bu/DDGl8n7t1Ob2DT1WVtaCGBoIYIjKtETvAQ8F3DalC5Ib+ODEp8Yl3HzeCZmIKfX F+9aRvKO4Q/ccttrYT+XuGu6JzzJSx8dlldZpNZAy8KDf3Vux0pJc96wy95VB5LoF42r swUkvdgVa8j38OQwToNTBQinp87cptwxdMYpD2tlgvpAaVJaeX3We4RsdfVL9e5XKzJl i611b2qI9b/nA4OSx4nk2qBpn+1toQf+zqPjY125jLOljC6dTAoz8q6msgCaGd5iFIkG C/bp5q76quyzPyOzq+kB6MAUs1Hx1ToVVPd4U4OiDeW+fys0N/JKbLjRCp7zHMYHimuQ QK3A== X-Gm-Message-State: AMke39mThgLkPi+B6kwtl/efdAUo72bcIdL5lxAc9xuRj4x45ZTLLuA4zH4eHFvyM/vTqdnc X-Received: by 10.223.151.135 with SMTP id s7mr8569614wrb.51.1486749597560; Fri, 10 Feb 2017 09:59:57 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 65sm544076wri.53.2017.02.10.09.59.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Feb 2017 09:59:56 -0800 (PST) Date: Fri, 10 Feb 2017 17:59:55 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, jiewen.yao@intel.com, feng.tian@intel.com, michael.d.kinney@intel.com, jeff.fan@intel.com, star.zeng@intel.com Message-ID: <20170210175955.GO16034@bivouac.eciton.net> References: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> <1486661891-7888-4-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1486661891-7888-4-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH 3/4] ArmPkg/CpuDxe: ARM: ignore page table updates that only change permissions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Feb 2017 17:59:59 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Feb 09, 2017 at 05:38:10PM +0000, Ard Biesheuvel wrote: > Currently, we have not implemented support on 32-bit ARM for managing > permission bits in the page tables. Since the new DXE page protection > for PE/COFF images may invoke EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() > with only permission attributes set, let's simply ignore those for now. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > index b6ba975b353a..89e429925ba9 100644 > --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > @@ -680,6 +680,13 @@ SetMemoryAttributes ( > { > EFI_STATUS Status; > > + // > + // Ignore invocations that only modify permission bits > + // > + if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { > + return EFI_SUCCESS; > + } > + > if(((BaseAddress & 0xFFFFF) == 0) && ((Length & 0xFFFFF) == 0)) { > // Is the base and length a multiple of 1 MB? > DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): MMU section 0x%x length 0x%x to %lx\n", (UINTN)BaseAddress, (UINTN)Length, Attributes)); > -- > 2.7.4 >