From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x235.google.com (mail-wr0-x235.google.com [IPv6:2a00:1450:400c:c0c::235]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0F26882035 for ; Fri, 10 Feb 2017 10:16:25 -0800 (PST) Received: by mail-wr0-x235.google.com with SMTP id o16so114055985wra.1 for ; Fri, 10 Feb 2017 10:16:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=n/pmzuO6NxtMvcaDs34OKZ3Mi0jum5GBUDZzt5lb0kY=; b=fCc9rMT8ETte97iAu8Kr9UuVU/9NLPZPRHeJj2gMhBYSIEky4ijB90Q4xyElebnuC+ e6wo8Sjht7txD0d5Ha0pK/x6wa3syHalZAWPgVGsZN8oRT1KHeJK+NI2mgla9u3Musll Jdho5YD6FB/PxyCIJWTv5lYpid5Sef9KCN9Nw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=n/pmzuO6NxtMvcaDs34OKZ3Mi0jum5GBUDZzt5lb0kY=; b=mCPLvP2Kk7EB9eyopcBPeBQXQCswAKZ30l1PeE5S37zQ+vZhbaarZpA92RQX3EVYpC XRj6N63/cjbyQsz5whwEPHKBMBWTX8R5sI95zP/0nwAEy4gmnHwA719l9Z5KQQ0Tx1+k k5g9wjZnGI1JWMO5yWlgHj9TfniI6wIjvFG9+/eWVbWTtVxNmP2awcxCzAztyEwJagRw J07yuvITghKk3gYkWHwKEqdXa4XvzYrtSf//W2c4pJoH+tkMJXACIeZXAPhvK1N9er3V SCCE0lOR0fMBflE7qwgqg8fJNcMrkL8V+l9MFnPHf9qkRKe0LrUucfM2yY3zBa1AfwOF zW7w== X-Gm-Message-State: AMke39ngA01RDfuk+9G4D7QeVMuPsj2nn4scEK/ETlqbe+qgsyKhCMiiYU04d/0BmMQAWq0i X-Received: by 10.223.133.226 with SMTP id 31mr8446221wru.137.1486750583633; Fri, 10 Feb 2017 10:16:23 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id h75sm3696501wrh.37.2017.02.10.10.16.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Feb 2017 10:16:22 -0800 (PST) Date: Fri, 10 Feb 2017 18:16:21 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, jiewen.yao@intel.com, feng.tian@intel.com, michael.d.kinney@intel.com, jeff.fan@intel.com, star.zeng@intel.com Message-ID: <20170210181621.GP16034@bivouac.eciton.net> References: <1486661891-7888-1-git-send-email-ard.biesheuvel@linaro.org> <1486661891-7888-5-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1486661891-7888-5-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH 4/4] ArmPkg/ArmMmuLib: AARCH64: add support for modifying only permissions X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Feb 2017 18:16:25 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Feb 09, 2017 at 05:38:11PM +0000, Ard Biesheuvel wrote: > Since the new DXE page protection for PE/COFF images may invoke > EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() with only permission > attributes set, add support for this in the AARCH64 MMU code. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 73 +++++++++++++++----- > 1 file changed, 56 insertions(+), 17 deletions(-) > > diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > index 6aa970bc0514..764e54b5d747 100644 > --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c > @@ -28,6 +28,10 @@ > // We use this index definition to define an invalid block entry > #define TT_ATTR_INDX_INVALID ((UINT32)~0) > > +#define EFI_MEMORY_CACHETYPE_MASK (EFI_MEMORY_UC | EFI_MEMORY_WC | \ > + EFI_MEMORY_WT | EFI_MEMORY_WB | \ > + EFI_MEMORY_UCE) > + This is already duplicated between ArmPkg/Drivers/CpuDxe/CpuDxe.h and UefiCpuPkg/CpuDxe/CpuDxe.h Can we avoid adding more? > STATIC > UINT64 > ArmMemoryAttributeToPageAttribute ( > @@ -101,25 +105,46 @@ PageAttributeToGcdAttribute ( > return GcdAttributes; > } > > -ARM_MEMORY_REGION_ATTRIBUTES > -GcdAttributeToArmAttribute ( > +STATIC > +UINT64 > +GcdAttributeToPageAttribute ( > IN UINT64 GcdAttributes > ) > { > - switch (GcdAttributes & 0xFF) { > + UINT64 PageAttributes; > + > + switch (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) { > case EFI_MEMORY_UC: > - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + PageAttributes = TT_ATTR_INDX_DEVICE_MEMORY; > + break; > case EFI_MEMORY_WC: > - return ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; > + PageAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; > + break; > case EFI_MEMORY_WT: > - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH; > + PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; These TT_SH additions look like a bugfix - should they be a separate commit? > + break; > case EFI_MEMORY_WB: > - return ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; > + PageAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; > + break; > default: > - DEBUG ((EFI_D_ERROR, "GcdAttributeToArmAttribute: 0x%lX attributes is not supported.\n", GcdAttributes)); > - ASSERT (0); > - return ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > + PageAttributes = TT_ATTR_INDX_MASK; OK, so you're doing the same thing here as in the ARM code. This is a substantial change in behaviour (old behaviour: if unknown, set to DEVICE; new behaviour: if unknown, set "all types permitted"). Am I missing something? > + break; > } > + > + if ((GcdAttributes & EFI_MEMORY_XP) != 0 || > + (GcdAttributes & EFI_MEMORY_CACHETYPE_MASK) == EFI_MEMORY_UC) { > + if (ArmReadCurrentEL () == AARCH64_EL2) { > + PageAttributes |= TT_XN_MASK; > + } else { > + PageAttributes |= TT_UXN_MASK | TT_PXN_MASK; > + } > + } > + > + if ((GcdAttributes & EFI_MEMORY_RO) != 0) { > + PageAttributes |= TT_AP_RO_RO; > + } > + > + return PageAttributes | TT_AF; > } > > #define MIN_T0SZ 16 > @@ -434,17 +459,31 @@ SetMemoryAttributes ( > ) > { > RETURN_STATUS Status; > - ARM_MEMORY_REGION_DESCRIPTOR MemoryRegion; > UINT64 *TranslationTable; > - > - MemoryRegion.PhysicalBase = BaseAddress; > - MemoryRegion.VirtualBase = BaseAddress; > - MemoryRegion.Length = Length; > - MemoryRegion.Attributes = GcdAttributeToArmAttribute (Attributes); > + UINT64 PageAttributes; > + UINT64 PageAttributeMask; > + > + PageAttributes = GcdAttributeToPageAttribute (Attributes); > + PageAttributeMask = 0; > + > + if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { > + // > + // No memory type was set in Attributes, so we are going to update the > + // permissions only. > + // > + PageAttributes &= TT_AP_MASK | TT_UXN_MASK | TT_PXN_MASK; > + PageAttributeMask = ~(TT_ADDRESS_MASK_BLOCK_ENTRY | TT_AP_MASK | > + TT_PXN_MASK | TT_XN_MASK); > + } > > TranslationTable = ArmGetTTBR0BaseAddress (); > > - Status = FillTranslationTable (TranslationTable, &MemoryRegion); > + Status = UpdateRegionMapping ( > + TranslationTable, > + BaseAddress, > + Length, > + PageAttributes, > + PageAttributeMask); > if (RETURN_ERROR (Status)) { > return Status; > } > -- > 2.7.4 >