From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22b.google.com (mail-wr0-x22b.google.com [IPv6:2a00:1450:400c:c0c::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AC1E882212 for ; Tue, 21 Feb 2017 06:00:51 -0800 (PST) Received: by mail-wr0-x22b.google.com with SMTP id 89so78058724wrr.3 for ; Tue, 21 Feb 2017 06:00:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=NCOpbr3MFC8PhzNH+04QhA8V2wCDDtzVR2xmtMFcZh8=; b=UwgwVuLYtMk1wiE2op9r3Yn5AaRiY4wVcT3PKpkph6ZlhcejnON9sD2QGEfkjpQtPz Mwjm0p+AXQlNUlS7/RmfxF0lyFZFjKKYhwXjxYFW2shhobZrT9IyAcW1vCCnCSxJu/Uo fIz7OUbkNP0lmFaApLF3lc0KFfwXRWW3wPEmc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=NCOpbr3MFC8PhzNH+04QhA8V2wCDDtzVR2xmtMFcZh8=; b=FmJAiW9FxKBaGkx4vW8/pWeEOTQtCVIWpmTXGathy9FrNSRuKVUQ47q2Stp1st4m1A 6d5lDNj8Y6yj2bCE1AcrBauG6gu5gftaQ6YMcPcuLjKJwE/aBW6N/ZEz5ryrQz7T883k r2sK9I3KHusj/mG50eyfmiPCS2CKme0WfHSgTYGNzSf2Gb4i51Wzm59XV8zt61A01Ybk Gyp8JDP25aZGEGOgBx1ngNaHf3Bf7/sO5DxCb/wSs1iw7PmuTUy+6uhH5q6oynS57Wqk cP3P+me0YKYiEjtdjuWUfepYjYSoHRj049mP4Lmi8jihrWKc05raCOdZCxcTsNKknfM5 XaJg== X-Gm-Message-State: AMke39l+S46Q9ZVU/MYWb3fxvCr7rf6IL3agH9uuVPGZlbN0FMfAJ3nBohsCZTBzN/yKEBbm X-Received: by 10.223.155.215 with SMTP id e23mr6226218wrc.133.1487685648848; Tue, 21 Feb 2017 06:00:48 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 10sm17702138wmi.23.2017.02.21.06.00.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 21 Feb 2017 06:00:48 -0800 (PST) Date: Tue, 21 Feb 2017 14:00:46 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, jiewen.yao@intel.com Message-ID: <20170221140046.GL16034@bivouac.eciton.net> References: <1487178716-24569-1-git-send-email-ard.biesheuvel@linaro.org> <1487178716-24569-3-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1487178716-24569-3-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v2 2/4] ArmPkg/CpuDxe: translate invalid memory types in EfiAttributeToArmAttribute X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 21 Feb 2017 14:00:52 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Feb 15, 2017 at 05:11:54PM +0000, Ard Biesheuvel wrote: > The single user of EfiAttributeToArmAttribute () is the protocol > method EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes(), which uses the > return value to compare against the ARM attributes of an existing mapping, > to infer whether it is actually necessary to change anything, or whether > the requested update is redundant. This saves some cache and TLB > maintenance on 32-bit ARM systems that use uncached translation tables. > > However, EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes() may be invoked with > only permission bits set, in which case the implied requested action is to > update the permissions of the region without modifying the cacheability > attributes. This is currently not possible, because > EfiAttributeToArmAttribute () ASSERT()s [on AArch64] on Attributes arguments > that lack a cacheability bit. > > So let's simply return TT_ATTR_INDX_MASK (AArch64) or > TT_DESCRIPTOR_SECTION_TYPE_FAULT (ARM) in these cases (or'ed with the > appropriate permission bits). This way, the return value is equally > suitable for checking whether the attributes need to be modified, but > in a way that accommodates the use without a cacheability bit set. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel With this updated commit message: Reviewed-by: Leif Lindholm > --- > ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 4 +--- > ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 3 --- > 2 files changed, 1 insertion(+), 6 deletions(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > index 15d5a8173233..7688846e70cb 100644 > --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > @@ -216,9 +216,7 @@ EfiAttributeToArmAttribute ( > ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK; > break; > default: > - DEBUG ((EFI_D_ERROR, "EfiAttributeToArmAttribute: 0x%lX attributes is not supported.\n", EfiAttributes)); > - ASSERT (0); > - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; > + ArmAttributes = TT_ATTR_INDX_MASK; > } > > // Set the access flag to match the block attributes > diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > index 6dcfba69e879..b6ba975b353a 100644 > --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > @@ -733,10 +733,7 @@ EfiAttributeToArmAttribute ( > > case EFI_MEMORY_UCE: > default: > - // Cannot be implemented UEFI definition unclear for ARM > - // Cause a page fault if these ranges are accessed. > ArmAttributes = TT_DESCRIPTOR_SECTION_TYPE_FAULT; > - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): Unsupported attribute %x will page fault on access\n", EfiAttributes)); > break; > } > > -- > 2.7.4 >