From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22b.google.com (mail-wm0-x22b.google.com [IPv6:2a00:1450:400c:c09::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6E4FA8222D for ; Wed, 22 Feb 2017 04:13:36 -0800 (PST) Received: by mail-wm0-x22b.google.com with SMTP id v186so138617418wmd.0 for ; Wed, 22 Feb 2017 04:13:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=UHVFP2De9f9KBFeUqM2S3NNvzQlk4KVoTdVH0pDs3OE=; b=MKEeWsx1tUURlsESrKXQ+Pq07mKmZ9BoTwfLYnN3sVuOruv4u3ajzgO9XRX+qcHvAq 1KTSwwWMozfBttF8UMNt3hwEMB2WANIc0aVemOl7XQqKskV3P95MI3f3OMkDtMuh6Fai zKwJ5bXr3/OAe6J/9MDwWBQ3oVLK6FjRsNqZk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=UHVFP2De9f9KBFeUqM2S3NNvzQlk4KVoTdVH0pDs3OE=; b=LoUKI/PkwNFo2zr/gf6eGrWYF3jAeyePt9M6/q1If5sr4PIuH71DwZO/J5sse6924L b0t1+kwCx1uae8xMJPITFuGqhcQdOd/HNl2cKaaaKgRFp720rR/7SXwl7ManD+YNqD9T 9ePe7lYWpkCG3jx+P4twJrG9psW6iWUipY77izGjpnhT29Zp95W5K0gdTrYGD3PvP16L ltQVJzoJzodpI/ijiMA1wB1Ky/HtLNm8Ibh6Hg1vCIdvxqXmCHvNuYfHqRGIY0C2Bi91 49sOBASRa8ibalgoNreWCNsHXzQVxHE9w3VwHHYKzjq31BtQ8hPgSbb6Kh3TOeaQ/sX2 zlWg== X-Gm-Message-State: AMke39lHfqOzWmwu9C9P31rjRtISTAMNUah70XhhqOgGg1mN999rVtn2YtIx9Da6+pm9aDU7 X-Received: by 10.28.49.70 with SMTP id x67mr2200186wmx.69.1487765614873; Wed, 22 Feb 2017 04:13:34 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id q5sm1514108wrd.32.2017.02.22.04.13.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Feb 2017 04:13:34 -0800 (PST) Date: Wed, 22 Feb 2017 12:13:32 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, heyi.guo@linaro.org Message-ID: <20170222121332.GS16034@bivouac.eciton.net> References: <1487756301-15646-1-git-send-email-ard.biesheuvel@linaro.org> <1487756301-15646-4-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1487756301-15646-4-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH 3/4] ArmPkg/ArmLib: AARCH64: allow the stack aligment (SA) bit to be managed X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Feb 2017 12:13:36 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Feb 22, 2017 at 09:38:20AM +0000, Ard Biesheuvel wrote: > In preparation of enabling stack alignment checking, which is mandated > by the UEFI spec for AARCH64, add the code to manage this bit to ArmLib. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > ArmPkg/Include/Chipset/AArch64.h | 12 +++++++ > ArmPkg/Library/ArmLib/AArch64/AArch64Support.S | 34 ++++++++++++++++++++ > 2 files changed, 46 insertions(+) > > diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h > index 9aecb1df81e0..cebfc5da426a 100644 > --- a/ArmPkg/Include/Chipset/AArch64.h > +++ b/ArmPkg/Include/Chipset/AArch64.h > @@ -194,6 +194,18 @@ ArmEnableAlignmentCheck ( > > VOID > EFIAPI > +ArmDisableStackAlignmentCheck ( > + VOID > + ); > + > +VOID > +EFIAPI > +ArmEnableStackAlignmentCheck ( > + VOID > + ); > + > +VOID > +EFIAPI > ArmDisableAllExceptions ( > VOID > ); > diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > index c35c05fdf681..e53b5fdc5986 100644 > --- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > +++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S > @@ -20,6 +20,7 @@ > .set CTRL_M_BIT, (1 << 0) > .set CTRL_A_BIT, (1 << 1) > .set CTRL_C_BIT, (1 << 2) > +.set CTRL_SA_BIT, (1 << 3) > .set CTRL_I_BIT, (1 << 12) > .set CTRL_V_BIT, (1 << 12) > .set CPACR_VFP_BITS, (3 << 20) > @@ -259,6 +260,39 @@ ASM_FUNC(ArmDisableAlignmentCheck) > isb > ret > > +ASM_FUNC(ArmEnableStackAlignmentCheck) > + EL1_OR_EL2(x1) > +1: mrs x0, sctlr_el1 // Get control register EL1 > + b 3f > +2: mrs x0, sctlr_el2 // Get control register EL2 > +3: orr x0, x0, #CTRL_SA_BIT // Set SA (stack alignment check) bit > + EL1_OR_EL2(x1) > +1: msr sctlr_el1, x0 // Write back control register > + b 3f > +2: msr sctlr_el2, x0 // Write back control register > +3: dsb sy > + isb > + ret > + > + > +ASM_FUNC(ArmDisableStackAlignmentCheck) > + EL1_OR_EL2_OR_EL3(x1) > +1: mrs x0, sctlr_el1 // Get control register EL1 > + b 4f > +2: mrs x0, sctlr_el2 // Get control register EL2 > + b 4f > +3: mrs x0, sctlr_el3 // Get control register EL3 > +4: bic x0, x0, #CTRL_SA_BIT // Clear SA (stack alignment check) bit > + EL1_OR_EL2_OR_EL3(x1) > +1: msr sctlr_el1, x0 // Write back control register > + b 4f > +2: msr sctlr_el2, x0 // Write back control register > + b 4f > +3: msr sctlr_el3, x0 // Write back control register > +4: dsb sy > + isb > + ret > + > > // Always turned on in AArch64. Else implementation specific. Leave in for C compatibility for now > ASM_FUNC(ArmEnableBranchPrediction) > -- > 2.7.4 >