From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0FB7881F5C for ; Sun, 26 Feb 2017 21:31:24 -0800 (PST) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP; 26 Feb 2017 21:31:23 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.35,212,1484035200"; d="scan'208";a="1115951511" Received: from jfan12-desk.ccr.corp.intel.com ([10.239.9.5]) by fmsmga001.fm.intel.com with ESMTP; 26 Feb 2017 21:31:22 -0800 From: Jeff Fan To: edk2-devel@lists.01.org Cc: Leo Duran , Feng Tian , Michael D Kinney Date: Mon, 27 Feb 2017 13:31:14 +0800 Message-Id: <20170227053114.5452-1-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 Subject: [PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Remove used SetCacheability() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 05:31:24 -0000 No one uses the internal function SetCacheability(). https://bugzilla.tianocore.org/show_bug.cgi?id=400 This updating is suggested by Leo' comments at https://www.mail-archive.com/edk2-devel@lists.01.org/msg22634.html Cc: Leo Duran Cc: Feng Tian Cc: Michael D Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 70 +---------------------------------- 1 file changed, 1 insertion(+), 69 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c index c7aa48b..b180b14 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -1,7 +1,7 @@ /** @file SMM MP service implementation -Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -827,74 +827,6 @@ Gen4GPageTable ( } /** - Set memory cache ability. - - @param PageTable PageTable Address - @param Address Memory Address to change cache ability - @param Cacheability Cache ability to set - -**/ -VOID -SetCacheability ( - IN UINT64 *PageTable, - IN UINTN Address, - IN UINT8 Cacheability - ) -{ - UINTN PTIndex; - VOID *NewPageTableAddress; - UINT64 *NewPageTable; - UINTN Index; - - ASSERT ((Address & EFI_PAGE_MASK) == 0); - - if (sizeof (UINTN) == sizeof (UINT64)) { - PTIndex = (UINTN)RShiftU64 (Address, 39) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - } - - PTIndex = (UINTN)RShiftU64 (Address, 30) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - - // - // A perfect implementation should check the original cacheability with the - // one being set, and break a 2M page entry into pieces only when they - // disagreed. - // - PTIndex = (UINTN)RShiftU64 (Address, 21) & 0x1ff; - if ((PageTable[PTIndex] & IA32_PG_PS) != 0) { - // - // Allocate a page from SMRAM - // - NewPageTableAddress = AllocatePageTableMemory (1); - ASSERT (NewPageTableAddress != NULL); - - NewPageTable = (UINT64 *)NewPageTableAddress; - - for (Index = 0; Index < 0x200; Index++) { - NewPageTable[Index] = PageTable[PTIndex]; - if ((NewPageTable[Index] & IA32_PG_PAT_2M) != 0) { - NewPageTable[Index] &= ~((UINT64)IA32_PG_PAT_2M); - NewPageTable[Index] |= (UINT64)IA32_PG_PAT_4K; - } - NewPageTable[Index] |= (UINT64)(Index << EFI_PAGE_SHIFT); - } - - PageTable[PTIndex] = ((UINTN)NewPageTableAddress & gPhyMask) | PAGE_ATTRIBUTE_BITS; - } - - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & gPhyMask); - - PTIndex = (UINTN)RShiftU64 (Address, 12) & 0x1ff; - ASSERT (PageTable[PTIndex] & IA32_PG_P); - PageTable[PTIndex] &= ~((UINT64)((IA32_PG_PAT_4K | IA32_PG_CD | IA32_PG_WT))); - PageTable[PTIndex] |= (UINT64)Cacheability; -} - -/** Schedule a procedure to run on the specified CPU. @param[in] Procedure The address of the procedure to run -- 2.9.3.windows.2