From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E4AAB81F40 for ; Mon, 27 Feb 2017 07:32:30 -0800 (PST) Received: by mail-wm0-x231.google.com with SMTP id u199so21692316wmd.1 for ; Mon, 27 Feb 2017 07:32:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=+OvvKsOTx7ZKcgvR3f37P3hMLEEmDYGxQQ//SJaZoa4=; b=ftNtjd39HrcoPEOFUImRieaUgdePRtaumaj4S2dEdDCNofoXcZw8uuJxsWFyKHfR4s SvER4m/Om3uKYY6ELKUhGFsVBOgfydsGMVa/bN7kMe1an0NXmzm0j4vQ1Tg3ZSoJMr+A KcWNAM/yufNYzxdguA8QLP+FM4K4sJwQ1/Eh0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=+OvvKsOTx7ZKcgvR3f37P3hMLEEmDYGxQQ//SJaZoa4=; b=TB8JjPdRJ3iSpYk6upg+PhCWa9EV1+Anwb088alQwLwuH6QgM0NUUtYvhifPBFa2tq wM7weu4AkG/Dq3nJRNQcw1j3awnvJc4JEjnZrLgVVnD2BiBEso1fI6+svhpq8/NWB2w3 KVN14Oe+ktysJvVkxiRlZzTXGtD6uvIobAfrKk/dRz0oYL3Ct7phH7Q3JYRnzHmX12ui KdcVhGmXr8NFfe5KyCpJTA5uVXqxx2dw8e91ZVcF3FXZ4dWc8J7WgeUaoT9j+AQG1Wd1 6tFS6RDnB+K+8rgVrHw5oqFnjNTk6tJZCHr6+JiOMio5AAT47eSGR+aZgF6cQPzTHxIH wgWg== X-Gm-Message-State: AMke39m12tueLmM7FGhhChUqGqkGAKDzm9ZaEVBl9cgECZs4S7ioX0VgasbqfRsNjQb5J403 X-Received: by 10.28.23.140 with SMTP id 134mr12022145wmx.23.1488209549432; Mon, 27 Feb 2017 07:32:29 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id d42sm22702219wrd.7.2017.02.27.07.32.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Feb 2017 07:32:28 -0800 (PST) Date: Mon, 27 Feb 2017 15:32:27 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, afish@apple.com, michael.d.kinney@intel.com, liming.gao@intel.com, jiewen.yao@intel.com, lersek@redhat.com, feng.tian@intel.com, star.zeng@intel.com Message-ID: <20170227153227.GD16034@bivouac.eciton.net> References: <1488206291-25768-1-git-send-email-ard.biesheuvel@linaro.org> <1488206291-25768-2-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1488206291-25768-2-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v4 1/7] ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 15:32:31 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Feb 27, 2017 at 02:38:05PM +0000, Ard Biesheuvel wrote: > To prevent the initial MMU->GCD memory space map synchronization from > stripping permissions attributes [which we cannot use in the GCD memory > space map, unfortunately], implement the same approach as x86, and ignore > SetMemoryAttributes() calls during the time SyncCacheConfig() is in > progress. This is a horrible hack, but is currently the only way we can > implement strict permissions on arbitrary memory regions [as opposed to > PE/COFF text/data sections only] Sounds like another excellent argument for why this CpuDxe should be cosying up with the UefiCpuPkg one longer-term. > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > Reviewed-by: Jiewen Yao > --- > ArmPkg/Drivers/CpuDxe/CpuDxe.c | 3 +++ > ArmPkg/Drivers/CpuDxe/CpuDxe.h | 1 + > ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 4 ++++ > 3 files changed, 8 insertions(+) > > diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c > index 5aa5b874144a..1955d1dece03 100644 > --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c > +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c > @@ -17,6 +17,7 @@ > > #include > > +BOOLEAN gIsFlushingGCD; OK, I am unable to not bikeshed this: The behaviour you're copying is implemented via a variable called mIsFlushingGCD. Why change the prefix? Surely we're not looking to export this variable any further in ARM? > > /** > This function flushes the range of addresses from Start to Start+Length > @@ -261,7 +262,9 @@ CpuDxeInitialize ( > // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go > // after the protocol is installed > // > + gIsFlushingGCD = TRUE; > SyncCacheConfig (&mCpu); > + gIsFlushingGCD = FALSE; > > // If the platform is a MPCore system then install the Configuration Table describing the > // secondary core states > diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h > index a00fc3064362..085e4cab2921 100644 > --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h > +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h > @@ -37,6 +37,7 @@ > #include > #include > > +extern BOOLEAN gIsFlushingGCD; Eew ... this suggest we are. / Leif > > /** > This function registers and enables the handler specified by InterruptHandler for a processor > diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > index ebe593d1c325..6dfec7e55888 100644 > --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > @@ -188,6 +188,10 @@ CpuSetMemoryAttributes ( > UINTN RegionLength; > UINTN RegionArmAttributes; > > + if (gIsFlushingGCD) { > + return EFI_SUCCESS; > + } > + > if ((BaseAddress & (SIZE_4KB - 1)) != 0) { > // Minimum granularity is SIZE_4KB (4KB on ARM) > DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes)); > -- > 2.7.4 >