From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x234.google.com (mail-wr0-x234.google.com [IPv6:2a00:1450:400c:c0c::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5A2D481F5B for ; Mon, 27 Feb 2017 07:39:02 -0800 (PST) Received: by mail-wr0-x234.google.com with SMTP id u108so24948093wrb.3 for ; Mon, 27 Feb 2017 07:39:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=XI1uKgQC0W3m5nEnrKLJvACm9nFRkkgMjHTL/xF5VKo=; b=jAF8Ck3zehwlhWpO4obyeM1MC0uWKNkLPJFlXlJ235aSELWj0Yk623z4TiD9V6oUSF O87yhMbRVlJp8/3VYRK4xIyZvGEVnyHRtEE14sB4ktyGFteQLD33oArFTtjVuK/jR5JO eW9R/PQQdSqdEvL7aZ4VnbhJV6+5xcqADRUJQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=XI1uKgQC0W3m5nEnrKLJvACm9nFRkkgMjHTL/xF5VKo=; b=oh+WQMDIuN/7os3MLEc1rBcONkKNTFfOGUWqA8T++KLpgzvlAUSnfYaOZJXOpWDSlK H3Z+4vy7VLKuxK+F3zwLrwDWwWVCsw909eOp6qyDadNQ4pkURLVOfVQigm/wqO7IMB5u 8Pnnl+SJszuoyTk2Pqf9AEPS54SIBjgOegHamOnSU82J0U/jT+QsUa/yRPwSx3gFZlAC KE65cGeuIkVTS3Sd8kNxdt0hYCXC76FWeD30WxyYDQNXYB19jmAvbP2zVbfmOH2r+f6L z733gPjo7E4Ml6rHX3iacFYit1N2vYgy9AGcko3IERm9e482ZNzJ9XWbzr2N+slTE8Q/ MmMA== X-Gm-Message-State: AMke39n5kwLJ/wkHiR4IdD9gFiC3zlf1gHTqAvC73GHYRwHR7ZWZpb7iVhRYU/9hJa5Vf15+ X-Received: by 10.223.179.15 with SMTP id j15mr14054382wrd.159.1488209940875; Mon, 27 Feb 2017 07:39:00 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 36sm22750287wrk.57.2017.02.27.07.38.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 27 Feb 2017 07:39:00 -0800 (PST) Date: Mon, 27 Feb 2017 15:38:58 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , "afish@apple.com" , "Kinney, Michael D" , "Gao, Liming" , "Yao, Jiewen" , Laszlo Ersek , "Tian, Feng" , "Zeng, Star" Message-ID: <20170227153858.GE16034@bivouac.eciton.net> References: <1488206291-25768-1-git-send-email-ard.biesheuvel@linaro.org> <1488206291-25768-2-git-send-email-ard.biesheuvel@linaro.org> <20170227153227.GD16034@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v4 1/7] ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 27 Feb 2017 15:39:02 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Feb 27, 2017 at 03:33:56PM +0000, Ard Biesheuvel wrote: > On 27 February 2017 at 15:32, Leif Lindholm wrote: > > On Mon, Feb 27, 2017 at 02:38:05PM +0000, Ard Biesheuvel wrote: > >> To prevent the initial MMU->GCD memory space map synchronization from > >> stripping permissions attributes [which we cannot use in the GCD memory > >> space map, unfortunately], implement the same approach as x86, and ignore > >> SetMemoryAttributes() calls during the time SyncCacheConfig() is in > >> progress. This is a horrible hack, but is currently the only way we can > >> implement strict permissions on arbitrary memory regions [as opposed to > >> PE/COFF text/data sections only] > > > > Sounds like another excellent argument for why this CpuDxe should be > > cosying up with the UefiCpuPkg one longer-term. > > > > I suppose so, yes. > > >> Contributed-under: TianoCore Contribution Agreement 1.0 > >> Signed-off-by: Ard Biesheuvel > >> Reviewed-by: Jiewen Yao > >> --- > >> ArmPkg/Drivers/CpuDxe/CpuDxe.c | 3 +++ > >> ArmPkg/Drivers/CpuDxe/CpuDxe.h | 1 + > >> ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c | 4 ++++ > >> 3 files changed, 8 insertions(+) > >> > >> diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c > >> index 5aa5b874144a..1955d1dece03 100644 > >> --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c > >> +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c > >> @@ -17,6 +17,7 @@ > >> > >> #include > >> > >> +BOOLEAN gIsFlushingGCD; > > > > OK, I am unable to not bikeshed this: > > The behaviour you're copying is implemented via a variable called > > mIsFlushingGCD. Why change the prefix? Surely we're not looking to > > export this variable any further in ARM? > > > > Because it is not local the one compilation unit, that's all. It is > not in a library, so in that sense, it is guaranteed to remain local > to this module, if that is any consolation. Ah, excellent. So, from how I read the coding standards (section 4.4), 'm' would still be the appropriate prefix: "A module variable is intended to only be accessed across a small set of related routines that have strict rules for accessing the data; in effect, constrained to the set of files described within a single .inf file." Regards, Leif > >> > >> /** > >> This function flushes the range of addresses from Start to Start+Length > >> @@ -261,7 +262,9 @@ CpuDxeInitialize ( > >> // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go > >> // after the protocol is installed > >> // > >> + gIsFlushingGCD = TRUE; > >> SyncCacheConfig (&mCpu); > >> + gIsFlushingGCD = FALSE; > >> > >> // If the platform is a MPCore system then install the Configuration Table describing the > >> // secondary core states > >> diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h > >> index a00fc3064362..085e4cab2921 100644 > >> --- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h > >> +++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h > >> @@ -37,6 +37,7 @@ > >> #include > >> #include > >> > >> +extern BOOLEAN gIsFlushingGCD; > > > > Eew ... this suggest we are. > > > > / > > Leif > > > >> > >> /** > >> This function registers and enables the handler specified by InterruptHandler for a processor > >> diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > >> index ebe593d1c325..6dfec7e55888 100644 > >> --- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > >> +++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c > >> @@ -188,6 +188,10 @@ CpuSetMemoryAttributes ( > >> UINTN RegionLength; > >> UINTN RegionArmAttributes; > >> > >> + if (gIsFlushingGCD) { > >> + return EFI_SUCCESS; > >> + } > >> + > >> if ((BaseAddress & (SIZE_4KB - 1)) != 0) { > >> // Minimum granularity is SIZE_4KB (4KB on ARM) > >> DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes)); > >> -- > >> 2.7.4 > >>