From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6301C80313 for ; Mon, 6 Mar 2017 06:48:38 -0800 (PST) Received: by mail-wm0-x22a.google.com with SMTP id t193so66471056wmt.1 for ; Mon, 06 Mar 2017 06:48:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=HgI8SeylBjV1tsG1TvFzY+R9Bf8bWQVWTPe+LGSFSc4=; b=DKaccvLjlVMRRZyi+gfm5MdWv0SfsqOmI4xweRLxGo59j32X/MV/hwV2PZ6X683SDn BLg3CX6nX6aOMUgUTwALpklsyTqf6PunNDIpEj6CIAgUJrXTf8W+BQSHMwzd2wjuh5qV Z2vUmqsNvCM/MD4eK6faVZdgZRtq+XE0CwyxM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=HgI8SeylBjV1tsG1TvFzY+R9Bf8bWQVWTPe+LGSFSc4=; b=CjVMwdbereJ8EK36hbHLKUpJP1jK7MXzGa36SgsZEF0MtAsQVYokeQaMeL1P0q/bb2 YLU71iOVM3MbLWUuwAb+5Jn9PHg/8eLxanScEbJ78JdeGsXV5K3eIAhvzVgLf6y827bh guf6GdzmhBbarCMcN9Ion+6j/63g5IHnGwj0kO23XxV/9UWjQ3X/pNrTn9ehxCuoPMaH jsQPMHkGJaj+oNt/+Rscj9qHea31NN2JEYWJuZQa4+w4RkyIYXzaUXvp2JEZk+1foCSo 9rkozE5YFmv3vDIxCwkLycC3Y++uKidz9x5TdcZNm8KfW0RBpq5Ze6YYYcOP5evc1es7 c3gQ== X-Gm-Message-State: AMke39kl71UNmbiVO2LwefiZlNWIObUofiqjNyZGg03fCF6JZ7cNATQwvtea8XuujYUKdZuX X-Received: by 10.28.35.66 with SMTP id j63mr4801792wmj.84.1488811716806; Mon, 06 Mar 2017 06:48:36 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 191sm15187411wmo.21.2017.03.06.06.48.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Mar 2017 06:48:36 -0800 (PST) Date: Mon, 6 Mar 2017 14:48:34 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, lersek@redhat.com Message-ID: <20170306144834.GV16034@bivouac.eciton.net> References: <1488450976-16257-1-git-send-email-ard.biesheuvel@linaro.org> <1488450976-16257-4-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1488450976-16257-4-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v2 3/4] ArmPkg/CpuDxe ARM: honour RO/XP attributes in SetMemoryAttributes() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 06 Mar 2017 14:48:38 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Mar 02, 2017 at 10:36:15AM +0000, Ard Biesheuvel wrote: > Enable the use of strict memory permissions on ARM by processing the > EFI_MEMORY_RO and EFI_MEMORY_XP rather than ignoring them. As before, > calls to CpuArchProtocol::SetMemoryAttributes that only set RO/XP > bits will preserve the cacheability attributes. Permissions attributes > are not preserved when setting the memory type only: the way the memory > permission attributes are defined does not allows for that, and so this > situation does not deviate from other architectures. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 151 ++++++++------------ > 1 file changed, 62 insertions(+), 89 deletions(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > index 26b637e7658f..6dd749dadf8b 100644 > --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > @@ -374,50 +374,41 @@ UpdatePageEntries ( > > // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone) > // EntryValue: values at bit positions specified by EntryMask > - EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK; > - EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE; > + EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK; > + if ((Attributes & EFI_MEMORY_XP) != 0) { > + EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN; > + } else { > + EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE; > + } > + > // Although the PI spec is unclear on this the GCD guarantees that only > // one Attribute bit is set at a time, so we can safely use a switch statement But the switch statement is going away. The change effectively introduces a guaranteed priority of interpretation if the spec is violated. Say something about this order being arbitrarily decided due to PI spce guarantee instead? > - switch (Attributes) { > - case EFI_MEMORY_UC: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > - // map to strongly ordered > - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 > - break; > - > - case EFI_MEMORY_WC: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > - // map to normal non-cachable > - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 > - break; > - > - case EFI_MEMORY_WT: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > - // write through with no-allocate > - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 > - break; > - > - case EFI_MEMORY_WB: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > - // write back (with allocate) > - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 > - break; > - > - case EFI_MEMORY_WP: > - case EFI_MEMORY_XP: > - case EFI_MEMORY_UCE: > - // cannot be implemented UEFI definition unclear for ARM > - // Cause a page fault if these ranges are accessed. > - EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT; > - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes)); > - break; > + if ((Attributes & EFI_MEMORY_UC) != 0) { Or should these be "Attributes & Mask" == "ATTRIBUTE"? > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > + // map to strongly ordered > + EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 > + } else if ((Attributes & EFI_MEMORY_WC) != 0) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > + // map to normal non-cachable > + EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 > + } else if ((Attributes & EFI_MEMORY_WT) != 0) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > + // write through with no-allocate > + EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 > + } else if ((Attributes & EFI_MEMORY_WB) != 0) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > + // write back (with allocate) > + EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 > + } > > - default: > - return EFI_UNSUPPORTED; Do we not want a fallback handling for the if-form as well? > + if ((Attributes & EFI_MEMORY_RO) != 0) { > + EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO; > + } else { > + EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW; > } > > // Obtain page table base > @@ -520,53 +511,42 @@ UpdateSectionEntries ( > // EntryValue: values at bit positions specified by EntryMask > > // Make sure we handle a section range that is unmapped > - EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK; > + EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN_MASK | > + TT_DESCRIPTOR_SECTION_AP_MASK; > EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION; > > // Although the PI spec is unclear on this the GCD guarantees that only > // one Attribute bit is set at a time, so we can safely use a switch statement Repeat of above. > - switch(Attributes) { > - case EFI_MEMORY_UC: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > - // map to strongly ordered > - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 > - break; > - > - case EFI_MEMORY_WC: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > - // map to normal non-cachable > - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 > - break; > - > - case EFI_MEMORY_WT: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > - // write through with no-allocate > - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 > - break; > - > - case EFI_MEMORY_WB: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > - // write back (with allocate) > - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 > - break; > - > - case EFI_MEMORY_WP: > - case EFI_MEMORY_XP: > - case EFI_MEMORY_RP: > - case EFI_MEMORY_UCE: > - // cannot be implemented UEFI definition unclear for ARM > - // Cause a page fault if these ranges are accessed. > - EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT; > - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes)); > - break; > + if ((Attributes & EFI_MEMORY_UC) != 0) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > + // map to strongly ordered > + EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 > + } else if ((Attributes & EFI_MEMORY_WC) != 0) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > + // map to normal non-cachable > + EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 > + } else if ((Attributes & EFI_MEMORY_WT) != 0) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > + // write through with no-allocate > + EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 > + } else if ((Attributes & EFI_MEMORY_WB) != 0) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > + // write back (with allocate) > + EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 > + } (Again, same questions as above.) > > + if ((Attributes & EFI_MEMORY_RO) != 0) { > + EntryValue |= TT_DESCRIPTOR_SECTION_AP_RO_RO; > + } else { > + EntryValue |= TT_DESCRIPTOR_SECTION_AP_RW_RW; > + } > > - default: > - return EFI_UNSUPPORTED; > + if ((Attributes & EFI_MEMORY_XP) != 0) { > + EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK; > } > > // obtain page table base > @@ -693,13 +673,6 @@ SetMemoryAttributes ( > UINT64 ChunkLength; > BOOLEAN FlushTlbs; > > - // > - // Ignore invocations that only modify permission bits > - // > - if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { > - return EFI_SUCCESS; > - } > - > FlushTlbs = FALSE; > while (Length > 0) { > if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) && > -- > 2.7.4 >