From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22b.google.com (mail-wr0-x22b.google.com [IPv6:2a00:1450:400c:c0c::22b]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3621F80349 for ; Mon, 6 Mar 2017 23:57:56 -0800 (PST) Received: by mail-wr0-x22b.google.com with SMTP id g10so132874705wrg.2 for ; Mon, 06 Mar 2017 23:57:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=VRPFMy7MNmWDn3mbVT610zc2EO/1YDtrEbPMmAn8t8g=; b=SfP4ZDbMFfjswjoS0Q22ZIwYb12+gKh0gjJFRhf/V2za0Hn5Pncy6MskJxPAhEwJNo e+bqzINwOnLFXqbTqaBsyIIuZNjgVwZaa6HU9tuZg3IQUR0EaJ76wNEU3eu+6bqMHbwj OroNN7JbsCaMaRfg2D8pgJ2xNYbjVyqsDeU/o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=VRPFMy7MNmWDn3mbVT610zc2EO/1YDtrEbPMmAn8t8g=; b=ft4H7yUv8x/pmXX3pX3Uk0k5a2oNNunJ7Pv7B0f1WLDgI5VQfa/iBi9VDMIpLEBFWP z3mNe0hrWP8r7lj6nmWzWBovrGY6/fa0cf95fwLF3tKg+l1NbP6jE5Es5626m0tfcD0g HfJRwL89AQAOokraC0Ir2LkGH3ihP81yttj775KMOV+gMW9cyWJlPGBpz3mUtWSd/I06 nEru+Hj2rc5Ckw+UtP0LDKF3cpynQKEGfkrl5xQTNh6u5cRRBrbzNNPq+xoZryAROx/Q PqQruTSRD4/UAsn3g1zH30vkczm6z9TC5NAWuiu9NOQoTferUf+G18EnTG84yIXzAOzI NLlg== X-Gm-Message-State: AMke39lM2gexfgQtLKfIKZhC7tqj1+0kbpDgRdtH0MflKKQtK/tBS2pJvG0tADNGw2PrxW1K X-Received: by 10.223.169.1 with SMTP id u1mr17800833wrc.53.1488873474109; Mon, 06 Mar 2017 23:57:54 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id s26sm29975146wra.66.2017.03.06.23.57.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 06 Mar 2017 23:57:53 -0800 (PST) Date: Tue, 7 Mar 2017 07:57:51 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, lersek@redhat.com Message-ID: <20170307075751.GD16034@bivouac.eciton.net> References: <1488821535-14795-1-git-send-email-ard.biesheuvel@linaro.org> <1488821535-14795-4-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1488821535-14795-4-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v3 3/4] ArmPkg/CpuDxe ARM: honour RO/XP attributes in SetMemoryAttributes() X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 07 Mar 2017 07:57:56 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Mar 06, 2017 at 06:32:14PM +0100, Ard Biesheuvel wrote: > Enable the use of strict memory permissions on ARM by processing the > EFI_MEMORY_RO and EFI_MEMORY_XP rather than ignoring them. As before, > calls to CpuArchProtocol::SetMemoryAttributes that only set RO/XP > bits will preserve the cacheability attributes. Permissions attributes > are not preserved when setting the memory type only: the way the memory > permission attributes are defined does not allows for that, and so this > situation does not deviate from other architectures. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > ArmPkg/Drivers/CpuDxe/Arm/Mmu.c | 178 ++++++++++---------- > 1 file changed, 86 insertions(+), 92 deletions(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > index a2993cf16a35..d3c307f48317 100644 > --- a/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/Arm/Mmu.c > @@ -19,6 +19,13 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > #include > #include "CpuDxe.h" > > +#define CACHE_ATTRIBUTE_MASK (EFI_MEMORY_UC | \ > + EFI_MEMORY_WC | \ > + EFI_MEMORY_WT | \ > + EFI_MEMORY_WB | \ > + EFI_MEMORY_UCE | \ > + EFI_MEMORY_WP) > + > // First Level Descriptors > typedef UINT32 ARM_FIRST_LEVEL_DESCRIPTOR; > > @@ -374,50 +381,48 @@ UpdatePageEntries ( > > // EntryMask: bitmask of values to change (1 = change this value, 0 = leave alone) > // EntryValue: values at bit positions specified by EntryMask > - EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK; > - EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE; > - // Although the PI spec is unclear on this the GCD guarantees that only > - // one Attribute bit is set at a time, so we can safely use a switch statement > - switch (Attributes) { > - case EFI_MEMORY_UC: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > - // map to strongly ordered > - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 > - break; > - > - case EFI_MEMORY_WC: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > - // map to normal non-cachable > - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 > - break; > - > - case EFI_MEMORY_WT: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > - // write through with no-allocate > - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 > - break; > - > - case EFI_MEMORY_WB: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > - // write back (with allocate) > - EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 > - break; > + EntryMask = TT_DESCRIPTOR_PAGE_TYPE_MASK | TT_DESCRIPTOR_PAGE_AP_MASK; > + if ((Attributes & EFI_MEMORY_XP) != 0) { > + EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE_XN; > + } else { > + EntryValue = TT_DESCRIPTOR_PAGE_TYPE_PAGE; > + } > > - case EFI_MEMORY_WP: > - case EFI_MEMORY_XP: > - case EFI_MEMORY_UCE: > - // cannot be implemented UEFI definition unclear for ARM > - // Cause a page fault if these ranges are accessed. > - EntryValue = TT_DESCRIPTOR_PAGE_TYPE_FAULT; > - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting page %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes)); > - break; > + // Although the PI spec is unclear on this, the GCD guarantees that only > + // one Attribute bit is set at a time, so the order of the conditionals below > + // is irrelevant. If no memory attribute is specified, we preserve whatever > + // memory type is set in the page tables, and update the permission attributes > + // only. > + if (Attributes & EFI_MEMORY_UC) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > + // map to strongly ordered > + EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 > + } else if (Attributes & EFI_MEMORY_WC) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > + // map to normal non-cachable > + EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 > + } else if (Attributes & EFI_MEMORY_WT) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > + // write through with no-allocate > + EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 > + } else if (Attributes & EFI_MEMORY_WB) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_MASK; > + // write back (with allocate) > + EntryValue |= TT_DESCRIPTOR_PAGE_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 > + } else if (Attributes & CACHE_ATTRIBUTE_MASK) { > + // catch unsupported memory type attributes > + ASSERT (FALSE); > + return EFI_UNSUPPORTED; > + } > > - default: > - return EFI_UNSUPPORTED; > + if ((Attributes & EFI_MEMORY_RO) != 0) { > + EntryValue |= TT_DESCRIPTOR_PAGE_AP_RO_RO; > + } else { > + EntryValue |= TT_DESCRIPTOR_PAGE_AP_RW_RW; > } > > // Obtain page table base > @@ -520,53 +525,49 @@ UpdateSectionEntries ( > // EntryValue: values at bit positions specified by EntryMask > > // Make sure we handle a section range that is unmapped > - EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK; > + EntryMask = TT_DESCRIPTOR_SECTION_TYPE_MASK | TT_DESCRIPTOR_SECTION_XN_MASK | > + TT_DESCRIPTOR_SECTION_AP_MASK; > EntryValue = TT_DESCRIPTOR_SECTION_TYPE_SECTION; > > - // Although the PI spec is unclear on this the GCD guarantees that only > - // one Attribute bit is set at a time, so we can safely use a switch statement > - switch(Attributes) { > - case EFI_MEMORY_UC: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > - // map to strongly ordered > - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 > - break; > - > - case EFI_MEMORY_WC: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > - // map to normal non-cachable > - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 > - break; > - > - case EFI_MEMORY_WT: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > - // write through with no-allocate > - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 > - break; > - > - case EFI_MEMORY_WB: > - // modify cacheability attributes > - EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > - // write back (with allocate) > - EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 > - break; > - > - case EFI_MEMORY_WP: > - case EFI_MEMORY_XP: > - case EFI_MEMORY_RP: > - case EFI_MEMORY_UCE: > - // cannot be implemented UEFI definition unclear for ARM > - // Cause a page fault if these ranges are accessed. > - EntryValue = TT_DESCRIPTOR_SECTION_TYPE_FAULT; > - DEBUG ((EFI_D_PAGE, "SetMemoryAttributes(): setting section %lx with unsupported attribute %x will page fault on access\n", BaseAddress, Attributes)); > - break; > + // Although the PI spec is unclear on this, the GCD guarantees that only > + // one Attribute bit is set at a time, so the order of the conditionals below > + // is irrelevant. If no memory attribute is specified, we preserve whatever > + // memory type is set in the page tables, and update the permission attributes > + // only. > + if (Attributes & EFI_MEMORY_UC) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > + // map to strongly ordered > + EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED; // TEX[2:0] = 0, C=0, B=0 > + } else if (Attributes & EFI_MEMORY_WC) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > + // map to normal non-cachable > + EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE; // TEX [2:0]= 001 = 0x2, B=0, C=0 > + } else if (Attributes & EFI_MEMORY_WT) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > + // write through with no-allocate > + EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC; // TEX [2:0] = 0, C=1, B=0 > + } else if (Attributes & EFI_MEMORY_WB) { > + // modify cacheability attributes > + EntryMask |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK; > + // write back (with allocate) > + EntryValue |= TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC; // TEX [2:0] = 001, C=1, B=1 > + } else if (Attributes & CACHE_ATTRIBUTE_MASK) { > + // catch unsupported memory type attributes > + ASSERT (FALSE); > + return EFI_UNSUPPORTED; > + } > > + if (Attributes & EFI_MEMORY_RO) { > + EntryValue |= TT_DESCRIPTOR_SECTION_AP_RO_RO; > + } else { > + EntryValue |= TT_DESCRIPTOR_SECTION_AP_RW_RW; > + } > > - default: > - return EFI_UNSUPPORTED; > + if (Attributes & EFI_MEMORY_XP) { > + EntryValue |= TT_DESCRIPTOR_SECTION_XN_MASK; > } > > // obtain page table base > @@ -697,13 +698,6 @@ SetMemoryAttributes ( > return EFI_SUCCESS; > } > > - // > - // Ignore invocations that only modify permission bits > - // > - if ((Attributes & EFI_MEMORY_CACHETYPE_MASK) == 0) { > - return EFI_SUCCESS; > - } > - > FlushTlbs = FALSE; > while (Length > 0) { > if ((BaseAddress % TT_DESCRIPTOR_SECTION_SIZE == 0) && > -- > 2.7.4 >