From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x232.google.com (mail-wr0-x232.google.com [IPv6:2a00:1450:400c:c0c::232]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4B9D780368 for ; Wed, 8 Mar 2017 05:10:25 -0800 (PST) Received: by mail-wr0-x232.google.com with SMTP id g10so22956987wrg.2 for ; Wed, 08 Mar 2017 05:10:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ENH491zf43C6nkUom5iu2utm5SBGwG0uXgGE1/g7YG0=; b=FfXZgto4SfxFoCrtP5KZuLfW9LxxWk6CkXDdVsw0O9RWBtnNmtBunS1FitMb5BythX qCGWtyMLy2rmvdy/oYEk3CUhn5gL0hE4o+7b5apgq2ZUsYpwzUigRA06qS8sph6lmYHC l0lsasrE+h0GfCr5P+AmqAqQkpa+FfAUG6kO8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ENH491zf43C6nkUom5iu2utm5SBGwG0uXgGE1/g7YG0=; b=uk0lGTm5V5bHUSNOgQZ9VWuw2pDZrmPQM7/9Iu9V5JZFpNc8gQ/Ssis4MAsI5Rsyu2 NvvXZEO85Uhhiab3xP+pxIVZjQQkeWDrXVvdq/tVznCxqghu68wh/oCWOBcwlsCTZbnt 2p9C4Qd7lVkChJELade5Vmb6wA2o+tj3Y1mp9Ih2t4Q5dWnUi+cX/9uCsdzdwJRq32/X K/WWyAbREpVbHhKCOztxUwdYE9IwPiGMFuNW68fXDbdS00zxzDcJnYN6QOtvBsSFb1t+ WNxmuiPDzMHPxCAcBGYTCBJD1AkN5bsfwHenFBsENozDNZO0ACgXseC0YBdJYDlYzVD3 a8eg== X-Gm-Message-State: AMke39nyk5nb7Aq0i2+z87lMBKrZ3W4fA7yLAhFLFgIyZo6qlOYx4ZkO3TTuPNLdD8NWtwsq X-Received: by 10.223.151.45 with SMTP id r42mr5175456wrb.185.1488978623750; Wed, 08 Mar 2017 05:10:23 -0800 (PST) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id g45sm4127586wrd.11.2017.03.08.05.10.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 08 Mar 2017 05:10:23 -0800 (PST) Date: Wed, 8 Mar 2017 13:10:21 +0000 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, heyi.guo@Linaro.org Message-ID: <20170308131021.GY16034@bivouac.eciton.net> References: <1488973904-15031-1-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1488973904-15031-1-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH] ArmPkg/CpuDxe: handle implied attributes in EfiAttributeToArmAttribute X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 08 Mar 2017 13:10:25 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Mar 08, 2017 at 12:51:44PM +0100, Ard Biesheuvel wrote: > Some memory attributes are implied by the memory type, e.g., device memory > is always mapped non-executable and cached memory should have the inner > shareable attribute. > > In order to prevent unnecessary memory attribute updates of mappings > created early on, make EfiAttributeToArmAttribute() return these implied > attributes in the same way as ArmMmuLib does already. This avoids false > positives when looking for differences between current and desired mapping > attributes. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm > --- > ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c | 10 +++++++--- > 1 file changed, 7 insertions(+), 3 deletions(-) > > diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > index 7688846e70cb..3e216c7cb235 100644 > --- a/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Mmu.c > @@ -204,16 +204,20 @@ EfiAttributeToArmAttribute ( > > switch (EfiAttributes & EFI_MEMORY_CACHETYPE_MASK) { > case EFI_MEMORY_UC: > - ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY; > + if (ArmReadCurrentEL () == AARCH64_EL2) { > + ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_XN_MASK; > + } else { > + ArmAttributes = TT_ATTR_INDX_DEVICE_MEMORY | TT_UXN_MASK | TT_PXN_MASK; > + } > break; > case EFI_MEMORY_WC: > ArmAttributes = TT_ATTR_INDX_MEMORY_NON_CACHEABLE; > break; > case EFI_MEMORY_WT: > - ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH; > + ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_THROUGH | TT_SH_INNER_SHAREABLE; > break; > case EFI_MEMORY_WB: > - ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK; > + ArmAttributes = TT_ATTR_INDX_MEMORY_WRITE_BACK | TT_SH_INNER_SHAREABLE; > break; > default: > ArmAttributes = TT_ATTR_INDX_MASK; > -- > 2.7.4 >