From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C1A1E80289 for ; Thu, 9 Mar 2017 00:36:07 -0800 (PST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Mar 2017 00:36:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,268,1486454400"; d="scan'208";a="1139930897" Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by fmsmga002.fm.intel.com with ESMTP; 09 Mar 2017 00:36:06 -0800 From: Jeff Fan To: edk2-devel@lists.01.org Cc: Feng Tian , Michael Kinney Date: Thu, 9 Mar 2017 16:35:43 +0800 Message-Id: <20170309083553.6016-2-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170309083553.6016-1-jeff.fan@intel.com> References: <20170309083553.6016-1-jeff.fan@intel.com> Subject: [PATCH 01/11] UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 09 Mar 2017 08:36:08 -0000 Current RegisterTableEntry filed in CPU_REGISTER_TABLE is one pointer to CPU_REGISTER_TABLE_ENTRY. If CPU register table wants to be passed from 32bit PEI to x64 DXE/SMM, x64 DXE/SMM cannot get the correct RegisterTableEntry. This update is to update RegisterTableEntry type to EFI_PHYSICAL_ADDRESS and make RegisterTableEntry is fixed length. Cc: Feng Tian Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 6 +++--- UefiCpuPkg/Include/AcpiCpuData.h | 6 +++--- UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 10 +++++----- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c index 3489b95..07c7102 100644 --- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c +++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c @@ -9,7 +9,7 @@ number of CPUs reported by the MP Services Protocol, so this module does not support hot plug CPUs. This module can be copied into a CPU specific package and customized if these additional features are required. -Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
Copyright (c) 2015, Red Hat, Inc. This program and the accompanying materials @@ -246,12 +246,12 @@ CpuS3DataInitialize ( RegisterTable[Index].InitialApicId = (UINT32)ProcessorInfoBuffer.ProcessorId; RegisterTable[Index].TableLength = 0; RegisterTable[Index].AllocatedSize = 0; - RegisterTable[Index].RegisterTableEntry = NULL; + RegisterTable[Index].RegisterTableEntry = 0; RegisterTable[NumberOfCpus + Index].InitialApicId = (UINT32)ProcessorInfoBuffer.ProcessorId; RegisterTable[NumberOfCpus + Index].TableLength = 0; RegisterTable[NumberOfCpus + Index].AllocatedSize = 0; - RegisterTable[NumberOfCpus + Index].RegisterTableEntry = NULL; + RegisterTable[NumberOfCpus + Index].RegisterTableEntry = 0; } AcpiCpuData->RegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTable; AcpiCpuData->PreSmmInitRegisterTable = (EFI_PHYSICAL_ADDRESS)(UINTN)(RegisterTable + NumberOfCpus); diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h index 12e9692..130eb90 100644 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ b/UefiCpuPkg/Include/AcpiCpuData.h @@ -1,7 +1,7 @@ /** @file Definitions for CPU S3 data. -Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.
+Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -55,10 +55,10 @@ typedef struct { // UINT32 InitialApicId; // - // Buffer of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be + // Physical address of CPU_REGISTER_TABLE_ENTRY structures. This buffer must be // allocated below 4GB from memory of type EfiACPIMemoryNVS. // - CPU_REGISTER_TABLE_ENTRY *RegisterTableEntry; + EFI_PHYSICAL_ADDRESS RegisterTableEntry; } CPU_REGISTER_TABLE; // diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index 532b7c4..12efc1f 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -1,7 +1,7 @@ /** @file Code for Processor S3 restoration -Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -826,13 +826,12 @@ CopyRegisterTable ( CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE)); for (Index = 0; Index < NumberOfCpus; Index++) { - DestinationRegisterTableList[Index].RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize); - ASSERT (DestinationRegisterTableList[Index].RegisterTableEntry != NULL); - CopyMem (DestinationRegisterTableList[Index].RegisterTableEntry, SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize); + RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize); + ASSERT (RegisterTableEntry != NULL); + CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize); // // Go though all MSRs in register table to initialize MSR spin lock // - RegisterTableEntry = DestinationRegisterTableList[Index].RegisterTableEntry; for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) { if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) { // @@ -841,6 +840,7 @@ CopyRegisterTable ( InitMsrSpinLockByIndex (RegisterTableEntry->Index); } } + DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry; } } -- 2.9.3.windows.2