From: Jeff Fan <jeff.fan@intel.com>
To: edk2-devel@lists.01.org
Cc: Feng Tian <feng.tian@intel.com>,
Michael Kinney <michael.d.kinney@intel.com>
Subject: [PATCH 03/11] UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0
Date: Thu, 9 Mar 2017 16:35:45 +0800 [thread overview]
Message-ID: <20170309083553.6016-4-jeff.fan@intel.com> (raw)
In-Reply-To: <20170309083553.6016-1-jeff.fan@intel.com>
Needn't to copy register table if AllocatedSize is 0.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 26 ++++++++++++++------------
1 file changed, 14 insertions(+), 12 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 12efc1f..f24d3d7 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -826,18 +826,20 @@ CopyRegisterTable (
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) {
- RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
- ASSERT (RegisterTableEntry != NULL);
- CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
- //
- // Go though all MSRs in register table to initialize MSR spin lock
- //
- for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
- if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
- //
- // Initialize MSR spin lock only for those MSRs need bit field writing
- //
- InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+ if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
+ RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
+ ASSERT (RegisterTableEntry != NULL);
+ CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
+ //
+ // Go though all MSRs in register table to initialize MSR spin lock
+ //
+ for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
+ if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
+ //
+ // Initialize MSR spin lock only for those MSRs need bit field writing
+ //
+ InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+ }
}
}
DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
--
2.9.3.windows.2
next prev parent reply other threads:[~2017-03-09 8:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-09 8:35 [PATCH 00/11] Add CPU features driver Jeff Fan
2017-03-09 8:35 ` [PATCH 01/11] UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type Jeff Fan
2017-03-09 8:35 ` [PATCH 02/11] UefiCpuPkg/CpuS3DataDxe: Consume the existing PcdCpuS3DataAddress Jeff Fan
2017-03-09 8:35 ` Jeff Fan [this message]
2017-03-09 8:35 ` [PATCH 04/11] UefiCpuPkg/Msr: Add CPUID signature check MACROs Jeff Fan
2017-03-09 8:35 ` [PATCH 05/11] UefiCpuPkg/UefiCpuPkg.dec: Add a set of CPU features PCDs Jeff Fan
2017-03-09 8:35 ` [PATCH 06/11] UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuid Jeff Fan
2017-03-09 8:35 ` [PATCH 07/11] UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuid Jeff Fan
2017-03-09 8:35 ` [PATCH 08/11] UefiCpuPkg/Include/Library: Add Register CPU Features Library Jeff Fan
2017-03-09 8:35 ` [PATCH 09/11] UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances Jeff Fan
2017-03-09 8:35 ` [PATCH 10/11] UefiCpuPkg: Add NULL CPU Common Features Library instance Jeff Fan
2017-03-09 8:35 ` [PATCH 11/11] UefiCpuPkg: Add CPU Features PEI/DXE drivers Jeff Fan
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