[PATCH 04/11] UefiCpuPkg/Msr: Add CPUID signature check MACROs

public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed

From: Jeff Fan <jeff.fan@intel.com>
To: edk2-devel@lists.01.org
Cc: Feng Tian <feng.tian@intel.com>,
	Michael Kinney <michael.d.kinney@intel.com>
Subject: [PATCH 04/11] UefiCpuPkg/Msr: Add CPUID signature check MACROs
Date: Thu,  9 Mar 2017 16:35:46 +0800	[thread overview]
Message-ID: <20170309083553.6016-5-jeff.fan@intel.com> (raw)
In-Reply-To: <20170309083553.6016-1-jeff.fan@intel.com>

All model-specific MSRs are related to processor signatures that are defined in
each section in Chapter 35 Model-Specific-Registers (MSR), Intel(R) 64 and
IA-32 Architectures Software Developer's Manual, Volume 3, September 2016.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/Include/Register/Msr/AtomMsr.h        | 22 +++++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h   | 21 ++++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/Core2Msr.h       | 19 ++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/CoreMsr.h        | 18 +++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h    | 18 +++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h    | 18 +++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/HaswellMsr.h     | 20 +++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h   | 18 +++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/NehalemMsr.h     | 21 ++++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/P6Msr.h          | 23 ++++++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h    | 15 ++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h    | 18 +++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/PentiumMsr.h     | 20 +++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h | 19 ++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h  | 22 +++++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h     | 19 ++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h    | 19 ++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/XeonDMsr.h       | 19 ++++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h      | 18 +++++++++++++++++-
 UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h     | 18 +++++++++++++++++-
 20 files changed, 365 insertions(+), 20 deletions(-)

diff --git a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
index c314195..b276469 100644
--- a/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/AtomMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,26 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel(R) Atom(TM) Processor Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_ATOM_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x1C || \
+    DisplayModel == 0x26 || \
+    DisplayModel == 0x27 || \
+    DisplayModel == 0x35 || \
+    DisplayModel == 0x36    \
+    )                       \
+   )
+
+/**
   Shared. Model Specific Platform ID (R).
 
   @param  ECX  MSR_ATOM_PLATFORM_ID (0x00000017)
diff --git a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
index 1c3c2dc..90bd523 100644
--- a/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/BroadwellMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,25 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel processors based on the Broadwell microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3D || \
+    DisplayModel == 0x47 || \
+    DisplayModel == 0x4F || \
+    DisplayModel == 0x56    \
+    )                       \
+   )
+
+/**
   Thread. See Table 35-2. See Section 18.4.2, "Global Counter Control
   Facilities.".
 
diff --git a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
index 9f0e790..9ebca5e 100644
--- a/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Core2Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel(R) Core(TM) 2 Processor Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_CORE2_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x0F || \
+    DisplayModel == 0x17    \
+    )                       \
+   )
+
+/**
   Shared. Model Specific Platform ID (R).
 
   @param  ECX  MSR_CORE2_PLATFORM_ID (0x00000017)
diff --git a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
index 0902aa9..4897c74 100644
--- a/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/CoreMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel Core Solo and Intel Core Duo Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_CORE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   ( \
+    DisplayModel == 0x0E \
+    ) \
+   )
+
+/**
   Unique. See Section 35.22, "MSRs in Pentium Processors," and see Table 35-2.
 
   @param  ECX  MSR_CORE_P5_MC_ADDR (0x00000000)
diff --git a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
index 58b9c57..5730918 100644
--- a/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/GoldmontMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel Atom processors based on the Goldmont microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_GOLDMONT_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x5C    \
+    )                       \
+   )
+
+/**
   Core. Control Features in Intel 64Processor (R/W).
 
   @param  ECX  MSR_GOLDMONT_FEATURE_CONTROL (0x0000003A)
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
index 7b190b5..b737a9e 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellEMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel processors based on the Haswell-E microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_HASWELL_E_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3F    \
+    )                       \
+   )
+
+/**
   Package. Configured State of Enabled Processor Core Count and Logical
   Processor Count (RO) -  After a Power-On RESET, enumerates factory
   configuration of the number of processor cores and logical processors in the
diff --git a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
index 8bf2c38..3cd1584 100644
--- a/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/HaswellMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,24 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel processors based on the Haswell microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_HASWELL_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3C || \
+    DisplayModel == 0x45 || \
+    DisplayModel == 0x46    \
+    )                       \
+   )
+
+/**
   Package.
 
   @param  ECX  MSR_HASWELL_PLATFORM_INFO (0x000000CE)
diff --git a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
index 41cbd2e..9eb0799 100644
--- a/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/IvyBridgeMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel processors based on the Ivy Bridge microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_IVY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x3A    \
+    )                       \
+   )
+
+/**
   Package. See http://biosbits.org.
 
   @param  ECX  MSR_IVY_BRIDGE_PLATFORM_INFO (0x000000CE)
diff --git a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
index 20e60df..94aebba 100644
--- a/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/NehalemMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,25 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel processors based on the Nehalem microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_NEHALEM_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x1A || \
+    DisplayModel == 0x1E || \
+    DisplayModel == 0x1F || \
+    DisplayModel == 0x2E    \
+    )                       \
+   )
+
+/**
   Package. Model Specific Platform ID (R).
 
   @param  ECX  MSR_NEHALEM_PLATFORM_ID (0x00000017)
diff --git a/UefiCpuPkg/Include/Register/Msr/P6Msr.h b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
index ef90800..aec2e2c 100644
--- a/UefiCpuPkg/Include/Register/Msr/P6Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/P6Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,27 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is P6 Family Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_P6_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x03 || \
+    DisplayModel == 0x05 || \
+    DisplayModel == 0x07 || \
+    DisplayModel == 0x08 || \
+    DisplayModel == 0x0A || \
+    DisplayModel == 0x0B \
+    ) \
+   )
+
+/**
   See Section 35.22, "MSRs in Pentium Processors.".
 
   @param  ECX  MSR_P6_P5_MC_ADDR (0x00000000)
diff --git a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
index 6cf68b2..8922d56 100644
--- a/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Pentium4Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,19 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Pentium(R) 4 Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_PENTIUM_4_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x0F \
+   )
+
+/**
   3, 4, 6. Shared. See Section 8.10.5, "Monitor/Mwait Address Range
   Determination.".
 
diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
index 294a381..70d54c8 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Pentium M Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_PENTIUM_M_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   ( \
+    DisplayModel == 0x0D \
+    ) \
+   )
+
+/**
   See Section 35.22, "MSRs in Pentium Processors.".
 
   @param  ECX  MSR_PENTIUM_M_P5_MC_ADDR (0x00000000)
diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
index cd846ea..9b2578b 100644
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,24 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Pentium Processors?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_PENTIUM_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x05 && \
+   (                        \
+    DisplayModel == 0x01 || \
+    DisplayModel == 0x02 || \
+    DisplayModel == 0x04    \
+    )                       \
+   )
+
+/**
   See Section 15.10.2, "Pentium Processor Machine-Check Exception Handling.".
 
   @param  ECX  MSR_PENTIUM_P5_MC_ADDR (0x00000000)
diff --git a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
index 1819ecb..c8a0b97 100644
--- a/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SandyBridgeMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel processors based on the Sandy Bridge microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x2A || \
+    DisplayModel == 0x2D    \
+    )                       \
+   )
+
+/**
   Thread. SMI Counter (R/O).
 
   @param  ECX  MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)
diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index b3b6b76..ec09bf3 100644
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,26 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel processors based on the Silvermont microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_SILVERMONT_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x37 || \
+    DisplayModel == 0x4A || \
+    DisplayModel == 0x4D || \
+    DisplayModel == 0x5A || \
+    DisplayModel == 0x5D    \
+    )                       \
+   )
+
+/**
   Module. Model Specific Platform ID (R).
 
   @param  ECX  MSR_SILVERMONT_PLATFORM_ID (0x00000017)
diff --git a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
index 23ca3e1..7166e5f 100644
--- a/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SkylakeMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel processors based on the Skylake microarchitecture?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_SKYLAKE_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x4E || \
+    DisplayModel == 0x5E    \
+    )                       \
+   )
+
+/**
   Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,
   RW if MSR_PLATFORM_INFO.[28] = 1.
 
diff --git a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
index ea22e22..ad7128a 100644
--- a/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/Xeon5600Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel(R) Xeon(R) Processor Series 5600?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x25 || \
+    DisplayModel == 0x2C    \
+    )                       \
+   )
+
+/**
   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
   handler to handle unsuccessful read of this MSR.
 
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
index 5e7e13a..7b31288 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonDMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,23 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel(R) Xeon(R) Processor D product Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x4F || \
+    DisplayModel == 0x56    \
+    )                       \
+   )
+
+/**
   Package. Protected Processor Inventory Number Enable Control (R/W).
 
   @param  ECX  MSR_XEON_D_PPIN_CTL (0x0000004E)
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
index d14ef21..d509660 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonE7Msr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel(R) Xeon(R) Processor E7 Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_XEON_E7_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x2F    \
+    )                       \
+   )
+
+/**
   Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP
   handler to handle unsuccessful read of this MSR.
 
diff --git a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
index 853d83b..43354d1 100644
--- a/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/XeonPhiMsr.h
@@ -6,7 +6,7 @@
   returned is a single 32-bit or 64-bit value, then a data structure is not
   provided for that MSR.
 
-  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
   which accompanies this distribution.  The full text of the license may be found at
@@ -27,6 +27,22 @@
 #include <Register/ArchitecturalMsr.h>
 
 /**
+  Is Intel(R) Xeon(R) Phi(TM) processor Family?
+
+  @param   DisplayFamily  Display Family ID
+  @param   DisplayModel   Display Model ID
+
+  @retval  TRUE   Yes, it is.
+  @retval  FALSE  No, it isn't.
+**/
+#define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \
+  (DisplayFamily == 0x06 && \
+   (                        \
+    DisplayModel == 0x57    \
+    )                       \
+   )
+
+/**
   Thread. SMI Counter (R/O).
 
   @param  ECX  MSR_XEON_PHI_SMI_COUNT (0x00000034)
-- 
2.9.3.windows.2

next prev parent reply	other threads:[~2017-03-09  8:36 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-09  8:35 [PATCH 00/11] Add CPU features driver Jeff Fan
2017-03-09  8:35 ` [PATCH 01/11] UefiCpuPkg/AcpiCpuData: Update RegisterTableEntry type Jeff Fan
2017-03-09  8:35 ` [PATCH 02/11] UefiCpuPkg/CpuS3DataDxe: Consume the existing PcdCpuS3DataAddress Jeff Fan
2017-03-09  8:35 ` [PATCH 03/11] UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0 Jeff Fan
2017-03-09  8:35 ` Jeff Fan [this message]
2017-03-09  8:35 ` [PATCH 05/11] UefiCpuPkg/UefiCpuPkg.dec: Add a set of CPU features PCDs Jeff Fan
2017-03-09  8:35 ` [PATCH 06/11] UefiCpuPkg: Add GUID gEdkiiCpuFeaturesSetDoneGuid Jeff Fan
2017-03-09  8:35 ` [PATCH 07/11] UefiCpuPkg: Add GUID gEdkiiCpuFeaturesInitDoneGuid Jeff Fan
2017-03-09  8:35 ` [PATCH 08/11] UefiCpuPkg/Include/Library: Add Register CPU Features Library Jeff Fan
2017-03-09  8:35 ` [PATCH 09/11] UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances Jeff Fan
2017-03-09  8:35 ` [PATCH 10/11] UefiCpuPkg: Add NULL CPU Common Features Library instance Jeff Fan
2017-03-09  8:35 ` [PATCH 11/11] UefiCpuPkg: Add CPU Features PEI/DXE drivers Jeff Fan

find likely ancestor, descendant, or conflicting patches for this message:
( dfblob:c314195 dfblob:b276469 dfblob:1c3c2dc dfblob:90bd523
dfblob:9f0e790 dfblob:9ebca5e dfblob:0902aa9 dfblob:4897c74
dfblob:58b9c57 dfblob:5730918 dfblob:7b190b5 dfblob:b737a9e
dfblob:8bf2c38 dfblob:3cd1584 dfblob:41cbd2e dfblob:9eb0799
dfblob:20e60df dfblob:94aebba dfblob:ef90800 dfblob:aec2e2c
dfblob:6cf68b2 dfblob:8922d56 dfblob:294a381 dfblob:70d54c8
dfblob:cd846ea dfblob:9b2578b dfblob:1819ecb dfblob:c8a0b97
dfblob:b3b6b76 dfblob:ec09bf3 dfblob:23ca3e1 dfblob:7166e5f
dfblob:ea22e22 dfblob:ad7128a dfblob:5e7e13a dfblob:7b31288
dfblob:d14ef21 dfblob:d509660 dfblob:853d83b dfblob:43354d1 )
 OR (
bs:"[PATCH 04/11] UefiCpuPkg/Msr: Add CPUID signature check MACROs" )
	(help)

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170309083553.6016-5-jeff.fan@intel.com \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

Be sure your reply has a Subject: header at the top and a blank line before the message body.

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox