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Date: Fri, 10 Mar 2017 15:21:42 +0000
From: Anthony PERARD <anthony.perard@citrix.com>
To: "Fan, Jeff" <jeff.fan@intel.com>
CC: "Yao, Jiewen" <jiewen.yao@intel.com>, "edk2-devel@lists.01.org"
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Subject: Re: [PATCH V4 1/3] UefiCpuPkg/CpuDxe: Add memory attribute setting.
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On Fri, Mar 10, 2017 at 01:02:22AM +0000, Fan, Jeff wrote:
> Anthony,
> 
> MSR 0x1A0 is architectural MSR defined in IA32 SDM.
> 
> Have you tried AMD real platform?

Yes, I did, and unless I've made a mistake, trying to read msr 0x1a0
does generate a GPF.

Also, I've now take a look into the AMD manuals[1] and more specificaly
"AMD64 Architecture Programmer’s Manual Volume 2: System
Programming"[2], there is no sign of MSR 0x1a0 (in Appendix A).

As for the XD bit on AMD, (well NX actually), it is describe at 5.6.3,
in the "Page Translation and Protection" chapter.


About MSR 0x1a0 been architectural defined, I guess that applies only to
Intel CPUs, all of them.

[1]: http://developer.amd.com/resources/developer-guides-manuals/
[2]: http://support.amd.com/TechDocs/24593.pdf

Thanks,

-- 
Anthony PERARD