From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x229.google.com (mail-wr0-x229.google.com [IPv6:2a00:1450:400c:c0c::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 972A48029A for ; Thu, 16 Mar 2017 07:19:53 -0700 (PDT) Received: by mail-wr0-x229.google.com with SMTP id g10so33063619wrg.2 for ; Thu, 16 Mar 2017 07:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=cum4LH76bou9/CZJaf2wMaa45JOO+EKQXB1NNLhOPlc=; b=g3zcxTK+HBhieJF5nUKk7Ev06FpDXhnjMIyYliETkx9QZpkU7IbucKEGHl3Ubz/tRF p0iqEj18lzO+F9zkzKcYwTCk8ymemA0hKB2yKtRmoU9DDBv81p1pvwXoROIWrvfZI3Qe aqAJIADauPt0bmx+5Miv8ATplD1478MGebvPc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=cum4LH76bou9/CZJaf2wMaa45JOO+EKQXB1NNLhOPlc=; b=kptpJwp3caopOMLT4xROjRh29C3lHVpWIq5yu9fp+p7LK/GBjQNDycOAUJ/2/kHi7h tvII4xOFyIQzXkRLu1nj3csWZ2vlpS8FoZvInsIusKXCHduqDmTWUu9OJ/bM9zEM+RAt o5TztSfJHUcJoqS3wYNztNJq9lj7aYq6jUq8E/veasd1engIi7/yiHzya7AjXTuBeUxo iWK2752YsoTc1CUVMJKpsXmGhW+IiY6GTfajE92IZnC8covqBXRBiEgwIV1/kmKrlgNm F+p1viBbYr8HwaDhRZoQDaZY2ieR1Z2fvsGCELoDqG+0Y3T7Qq4Cbxq1NVuFLeCtcuFv 1mHg== X-Gm-Message-State: AFeK/H3WqHWNfgASBFxEYj9HkGQ1nQxrGCUecanvfWybnzU1G0rNarpBXUbcYm2mN5bwYVUj X-Received: by 10.223.175.15 with SMTP id z15mr9548663wrc.84.1489673992046; Thu, 16 Mar 2017 07:19:52 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id x133sm4490867wme.22.2017.03.16.07.19.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Mar 2017 07:19:51 -0700 (PDT) Date: Thu, 16 Mar 2017 14:19:49 +0000 From: Leif Lindholm To: Jeremy Linton Cc: edk2-devel@lists.01.org, ryan.harkin@linaro.org, linaro-uefi@lists.linaro.org, ard.biesheuvel@linaro.org Message-ID: <20170316141949.GF16034@bivouac.eciton.net> References: <20170307221512.5180-1-jeremy.linton@arm.com> <20170307221512.5180-4-jeremy.linton@arm.com> MIME-Version: 1.0 In-Reply-To: <20170307221512.5180-4-jeremy.linton@arm.com> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v4 3/6] EmbeddedPkg: SiI3132: Add SCSI protocol support to header X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Mar 2017 14:19:54 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Mar 07, 2017 at 04:15:08PM -0600, Jeremy Linton wrote: > Add EXT_SCSI_PASS_THRU structures to SI3132_PORT structure, > along with helpers and new entry points. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jeremy Linton LGTM Reviewed-by: Leif Lindholm > --- > EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h | 103 ++++++++++++++++++++--- > 1 file changed, 93 insertions(+), 10 deletions(-) > > diff --git a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h > index a7bc956..99c2f26 100644 > --- a/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h > +++ b/EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132.h > @@ -1,7 +1,7 @@ > /** @file > * Header containing the structure specific to the Silicon Image I3132 Sata PCI card > * > -* Copyright (c) 2011-2015, ARM Limited. All rights reserved. > +* Copyright (c) 2011-2017, ARM Limited. All rights reserved. > * > * This program and the accompanying materials > * are licensed and made available under the terms and conditions of the BSD License > @@ -20,6 +20,7 @@ > > #include > #include > +#include > > #include > #include > @@ -57,6 +58,7 @@ > #define SII3132_PORT_SLOTSTATUS_REG 0x1800 > #define SII3132_PORT_CMDACTIV_REG 0x1C00 > #define SII3132_PORT_SSTATUS_REG 0x1F04 > +#define SII3132_PORT_SERROR_REG 0x1F08 > > #define SII3132_PORT_CONTROL_RESET (1 << 0) > #define SII3132_PORT_DEVICE_RESET (1 << 1) > @@ -81,6 +83,7 @@ > #define PRB_CTRL_INT_MASK 0x40 > #define PRB_CTRL_SRST 0x80 > > +#define PRB_PROT_DEFAULT 0x00 > #define PRB_PROT_PACKET 0x01 > #define PRB_PROT_LEGACY_QUEUE 0x02 > #define PRB_PROT_NATIVE_QUEUE 0x04 > @@ -88,11 +91,18 @@ > #define PRB_PROT_WRITE 0x10 > #define PRB_PROT_TRANSPARENT 0x20 > > +#define SII_FIS_REGISTER_H2D 0x27 //Register FIS - Host to Device > +#define SII_FIS_CONTROL_CMD (1 << 7) //Indicate FIS is a command > + > #define SGE_XCF (1 << 28) > #define SGE_DRD (1 << 29) > #define SGE_LNK (1 << 30) > #define SGE_TRM 0x80000000 > > +#define SI_MAX_CDB 12 //MAX supported CDB > +#define SI_MAX_SENSE 256 > +#define SI_DEFAULT_TIMEOUT 50000 > + > typedef struct _SATA_SI3132_SGE { > UINT32 DataAddressLow; > UINT32 DataAddressHigh; > @@ -121,6 +131,8 @@ typedef struct _SATA_SI3132_DEVICE { > UINTN Index; > struct _SATA_SI3132_PORT *Port; //Parent Port > UINT32 BlockSize; > + BOOLEAN Atapi; //ATAPI device > + BOOLEAN Cdb16; //Uses 16byte CDB transfers (or 12) > } SATA_SI3132_DEVICE; > > typedef struct _SATA_SI3132_PORT { > @@ -137,17 +149,19 @@ typedef struct _SATA_SI3132_PORT { > } SATA_SI3132_PORT; > > typedef struct _SATA_SI3132_INSTANCE { > - UINTN Signature; > - > - SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT]; > - > - EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol; > - > - EFI_PCI_IO_PROTOCOL *PciIo; > + UINTN Signature; > + > + SATA_SI3132_PORT Ports[SATA_SII3132_MAXPORT]; > + EFI_ATA_PASS_THRU_MODE AtaPassThruMode; > + EFI_ATA_PASS_THRU_PROTOCOL AtaPassThruProtocol; > + EFI_EXT_SCSI_PASS_THRU_MODE ExtScsiPassThruMode; > + EFI_EXT_SCSI_PASS_THRU_PROTOCOL ExtScsiPassThru; > + EFI_PCI_IO_PROTOCOL *PciIo; > } SATA_SI3132_INSTANCE; > > #define SATA_SII3132_SIGNATURE SIGNATURE_32('s', 'i', '3', '2') > -#define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR(a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE) > +#define INSTANCE_FROM_ATAPASSTHRU_THIS(a) CR (a, SATA_SI3132_INSTANCE, AtaPassThruProtocol, SATA_SII3132_SIGNATURE) > +#define INSTANCE_FROM_SCSIPASSTHRU_THIS(a) CR (a, SATA_SI3132_INSTANCE, ExtScsiPassThru, SATA_SII3132_SIGNATURE) > > #define SATA_GLOBAL_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, Value) > #define SATA_GLOBAL_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 0, Offset, 1, &Value32); } > @@ -155,7 +169,7 @@ typedef struct _SATA_SI3132_INSTANCE { > #define SATA_PORT_READ32(Offset, Value) PciIo->Mem.Read (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, Value) > #define SATA_PORT_WRITE32(Offset, Value) { UINT32 Value32 = Value; PciIo->Mem.Write (PciIo, EfiPciIoWidthUint32, 1, Offset, 1, &Value32); } > > -#define SATA_TRACE(txt) DEBUG((EFI_D_VERBOSE, "ARM_SATA: " txt "\n")) > +#define SATA_TRACE(txt) DEBUG ((DEBUG_VERBOSE, "ARM_SATA: " txt "\n")) > > extern EFI_COMPONENT_NAME_PROTOCOL gSataSiI3132ComponentName; > extern EFI_COMPONENT_NAME2_PROTOCOL gSataSiI3132ComponentName2; > @@ -266,4 +280,73 @@ EFI_STATUS SiI3132ResetDevice ( > IN UINT16 PortMultiplierPort > ); > > +/** > + * EFI ATA Pass Thru Entry points for SCSI Protocol > + */ > +SATA_SI3132_DEVICE* GetSataDevice ( > + IN SATA_SI3132_INSTANCE *SataInstance, > + IN UINT16 Port, > + IN UINT16 PortMultiplierPort > + ); > + > +EFI_STATUS SiI3132IssueCommand ( > + IN SATA_SI3132_PORT *SataPort, > + EFI_PCI_IO_PROTOCOL *PciIo, > + IN UINT32 Timeout, > + VOID *StatusBlock > + ); > + > +/** > + * EFI SCSI Pass Thru Protocol > + */ > +EFI_STATUS SiI3132ScsiPassThru ( > + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, > + IN UINT8 *Target, > + IN UINT64 Lun, > + IN OUT EFI_EXT_SCSI_PASS_THRU_SCSI_REQUEST_PACKET *Packet, > + IN EFI_EVENT Event OPTIONAL > + ); > + > +EFI_STATUS SiI3132GetNextTargetLun ( > + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, > + IN OUT UINT8 **Target, > + IN OUT UINT64 *Lun > +); > + > +EFI_STATUS SiI3132GetNextTargetLun2 ( > + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, > + IN UINT8 *Target, > + IN UINT64 Lun, > + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath > + ); > + > +EFI_STATUS SiI3132ScsiBuildDevicePath ( > + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, > + IN UINT8 *Target, > + IN UINT64 Lun, > + IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath > + ); > + > +EFI_STATUS SiI3132GetTargetLun ( > + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, > + IN EFI_DEVICE_PATH_PROTOCOL *DevicePath, > + OUT UINT8 **Target, > + OUT UINT64 *Lun > + ); > + > +EFI_STATUS SiI3132ResetChannel ( > + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This > + ); > + > +EFI_STATUS SiI3132ResetTargetLun ( > + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, > + IN UINT8 *Target, > + IN UINT64 Lun > + ); > + > +EFI_STATUS SiI3132GetNextTarget ( > + IN EFI_EXT_SCSI_PASS_THRU_PROTOCOL *This, > + IN OUT UINT8 **Target > + ); > + > #endif > -- > 2.9.3 >