From: Jeff Fan <jeff.fan@intel.com>
To: edk2-devel@lists.01.org
Cc: Feng Tian <feng.tian@intel.com>,
Michael Kinney <michael.d.kinney@intel.com>
Subject: [PATCH v4 03/11] UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0
Date: Fri, 17 Mar 2017 13:49:19 +0800 [thread overview]
Message-ID: <20170317054921.12204-2-jeff.fan@intel.com> (raw)
In-Reply-To: <20170317054921.12204-1-jeff.fan@intel.com>
Needn't to copy register table if AllocatedSize is 0.
v4:
Fix potential uninitialized variable issue.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 27 +++++++++++++++------------
1 file changed, 15 insertions(+), 12 deletions(-)
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 12efc1f..2588979 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -826,18 +826,21 @@ CopyRegisterTable (
CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
for (Index = 0; Index < NumberOfCpus; Index++) {
- RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
- ASSERT (RegisterTableEntry != NULL);
- CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
- //
- // Go though all MSRs in register table to initialize MSR spin lock
- //
- for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
- if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
- //
- // Initialize MSR spin lock only for those MSRs need bit field writing
- //
- InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+ RegisterTableEntry = NULL;
+ if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
+ RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
+ ASSERT (RegisterTableEntry != NULL);
+ CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
+ //
+ // Go though all MSRs in register table to initialize MSR spin lock
+ //
+ for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
+ if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
+ //
+ // Initialize MSR spin lock only for those MSRs need bit field writing
+ //
+ InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+ }
}
}
DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
--
2.9.3.windows.2
next prev parent reply other threads:[~2017-03-17 5:49 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-17 5:49 [PATCH v4 00/11] Add CPU features driver Jeff Fan
2017-03-17 5:49 ` Jeff Fan [this message]
2017-03-17 5:49 ` [PATCH v4 08/11] UefiCpuPkg/Include/Library: Add Register CPU Features Library Jeff Fan
2017-03-17 5:49 ` [PATCH v4 09/11] UefiCpuPkg: Add PEI/DXE Register CPU Features Library instances Jeff Fan
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