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From: Jeff Fan <jeff.fan@intel.com>
To: edk2-devel@lists.01.org
Cc: Feng Tian <feng.tian@intel.com>,
	Michael Kinney <michael.d.kinney@intel.com>
Subject: [PATCH v5 03/11] UefiCpuPkg/PiSmmCpuDxeSmm: Skip if AllocatedSize is 0
Date: Mon, 20 Mar 2017 16:19:38 +0800	[thread overview]
Message-ID: <20170320081939.6196-2-jeff.fan@intel.com> (raw)
In-Reply-To: <20170320081939.6196-1-jeff.fan@intel.com>

Needn't to copy register table if AllocatedSize is 0.

v4:
  Fix potential uninitialized variable issue.

v5:
  Set DestinationRegisterTableList[Index].RegisterTableEntry before
  RegisterTableEntry is updated.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 30 +++++++++++++++++-------------
 1 file changed, 17 insertions(+), 13 deletions(-)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index 12efc1f..c3280b8 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -826,21 +826,25 @@ CopyRegisterTable (
 
   CopyMem (DestinationRegisterTableList, SourceRegisterTableList, NumberOfCpus * sizeof (CPU_REGISTER_TABLE));
   for (Index = 0; Index < NumberOfCpus; Index++) {
-    RegisterTableEntry = AllocatePool (DestinationRegisterTableList[Index].AllocatedSize);
-    ASSERT (RegisterTableEntry != NULL);
-    CopyMem (RegisterTableEntry, (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry, DestinationRegisterTableList[Index].AllocatedSize);
-    //
-    // Go though all MSRs in register table to initialize MSR spin lock
-    //
-    for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
-      if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
-        //
-        // Initialize MSR spin lock only for those MSRs need bit field writing
-        //
-        InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+    if (DestinationRegisterTableList[Index].AllocatedSize != 0) {
+      RegisterTableEntry = AllocateCopyPool (
+        DestinationRegisterTableList[Index].AllocatedSize,
+        (VOID *)(UINTN)SourceRegisterTableList[Index].RegisterTableEntry
+        );
+      ASSERT (RegisterTableEntry != NULL);
+      DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
+      //
+      // Go though all MSRs in register table to initialize MSR spin lock
+      //
+      for (Index1 = 0; Index1 < DestinationRegisterTableList[Index].TableLength; Index1++, RegisterTableEntry++) {
+        if ((RegisterTableEntry->RegisterType == Msr) && (RegisterTableEntry->ValidBitLength < 64)) {
+          //
+          // Initialize MSR spin lock only for those MSRs need bit field writing
+          //
+          InitMsrSpinLockByIndex (RegisterTableEntry->Index);
+        }
       }
     }
-    DestinationRegisterTableList[Index].RegisterTableEntry = (EFI_PHYSICAL_ADDRESS)(UINTN)RegisterTableEntry;
   }
 }
 
-- 
2.9.3.windows.2



  reply	other threads:[~2017-03-20  8:19 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-20  8:19 [PATCH v5 00/11] Add CPU features driver Jeff Fan
2017-03-20  8:19 ` Jeff Fan [this message]
2017-03-20  8:19 ` [PATCH v5 10/11] UefiCpuPkg: Add NULL CPU Common Features Library instance Jeff Fan
2017-03-20  8:26 ` Do edk2 have plan to implement EFI_REST_PROTOCOL ? wang xiaofeng
2017-03-21  8:07 ` [PATCH v5 00/11] Add CPU features driver Tian, Feng

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