* [PATCH 1/2] UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64
2017-03-23 5:27 [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table Jeff Fan
@ 2017-03-23 5:27 ` Jeff Fan
2017-03-23 5:27 ` [PATCH 2/2] UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address Jeff Fan
2017-03-27 5:30 ` [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table Tian, Feng
2 siblings, 0 replies; 4+ messages in thread
From: Jeff Fan @ 2017-03-23 5:27 UTC (permalink / raw)
To: edk2-devel; +Cc: Feng Tian, Michael Kinney
The input parameter Index of PreSmmCpuRegisterTableWrite() and
CpuRegisterTableWrite() is defined as UINT32. Index is MSR/MMIO address that
will be saved in CPU register table. UINT32 blocks the MMIO address > 4GB.
This fix is to define Index to UINT64 instead of UINT32.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 4 ++--
.../Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
index 42eb3b2..3fb8209 100644
--- a/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
+++ b/UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h
@@ -366,7 +366,7 @@ EFIAPI
CpuRegisterTableWrite (
IN UINTN ProcessorNumber,
IN REGISTER_TYPE RegisterType,
- IN UINT32 Index,
+ IN UINT64 Index,
IN UINT64 ValueMask,
IN UINT64 Value
);
@@ -390,7 +390,7 @@ EFIAPI
PreSmmCpuRegisterTableWrite (
IN UINTN ProcessorNumber,
IN REGISTER_TYPE RegisterType,
- IN UINT32 Index,
+ IN UINT64 Index,
IN UINT64 ValueMask,
IN UINT64 Value
);
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index 396618b..32189cb 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -506,7 +506,7 @@ CpuRegisterTableWriteWorker (
IN BOOLEAN PreSmmFlag,
IN UINTN ProcessorNumber,
IN REGISTER_TYPE RegisterType,
- IN UINT32 Index,
+ IN UINT64 Index,
IN UINT8 ValidBitStart,
IN UINT8 ValidBitLength,
IN UINT64 Value
@@ -550,7 +550,7 @@ CpuRegisterTableWriteWorker (
//
RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
RegisterTableEntry[RegisterTable->TableLength].RegisterType = RegisterType;
- RegisterTableEntry[RegisterTable->TableLength].Index = Index;
+ RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32) Index;
RegisterTableEntry[RegisterTable->TableLength].ValidBitStart = ValidBitStart;
RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength;
RegisterTableEntry[RegisterTable->TableLength].Value = Value;
@@ -577,7 +577,7 @@ EFIAPI
CpuRegisterTableWrite (
IN UINTN ProcessorNumber,
IN REGISTER_TYPE RegisterType,
- IN UINT32 Index,
+ IN UINT64 Index,
IN UINT64 ValueMask,
IN UINT64 Value
)
@@ -611,7 +611,7 @@ EFIAPI
PreSmmCpuRegisterTableWrite (
IN UINTN ProcessorNumber,
IN REGISTER_TYPE RegisterType,
- IN UINT32 Index,
+ IN UINT64 Index,
IN UINT64 ValueMask,
IN UINT64 Value
)
--
2.9.3.windows.2
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address
2017-03-23 5:27 [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table Jeff Fan
2017-03-23 5:27 ` [PATCH 1/2] UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64 Jeff Fan
@ 2017-03-23 5:27 ` Jeff Fan
2017-03-27 5:30 ` [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table Tian, Feng
2 siblings, 0 replies; 4+ messages in thread
From: Jeff Fan @ 2017-03-23 5:27 UTC (permalink / raw)
To: edk2-devel; +Cc: Feng Tian, Michael Kinney
The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to
indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 type
actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB.
This update on CPU_REGISTER_TABLE_ENTRY is to add additional UINT32 field
HighIndex to indicate the high 32bit MMIO address and original Index still
indicate the low 32bit MMIO address.
This update makes use of original padding space between ValidBitLength and
Value to add HighIndex.
Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
---
UefiCpuPkg/Include/AcpiCpuData.h | 12 +++++++-----
.../Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 6 +++---
.../Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 1 +
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 2 +-
4 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h
index 130eb90..ec09207 100644
--- a/UefiCpuPkg/Include/AcpiCpuData.h
+++ b/UefiCpuPkg/Include/AcpiCpuData.h
@@ -29,11 +29,13 @@ typedef enum {
// Element of register table entry
//
typedef struct {
- REGISTER_TYPE RegisterType;
- UINT32 Index;
- UINT8 ValidBitStart;
- UINT8 ValidBitLength;
- UINT64 Value;
+ REGISTER_TYPE RegisterType; // offset 0 - 3
+ UINT32 Index; // offset 4 - 7
+ UINT8 ValidBitStart; // offset 8
+ UINT8 ValidBitLength; // offset 9
+ UINT16 Reserved; // offset 10 - 11
+ UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped
+ UINT64 Value; // offset 16-23
} CPU_REGISTER_TABLE_ENTRY;
//
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
index d879591..34e6c6b 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c
@@ -370,9 +370,9 @@ DumpRegisterTableOnProcessor (
case MemoryMapped:
DEBUG ((
DebugPrintErrorLevel,
- "Processor: %d: MMIO: %x, Bit Start: %d, Bit Length: %d, Value: %lx\r\n",
+ "Processor: %d: MMIO: %lx, Bit Start: %d, Bit Length: %d, Value: %lx\r\n",
ProcessorNumber,
- RegisterTableEntry->Index,
+ RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32),
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitLength,
RegisterTableEntry->Value
@@ -628,7 +628,7 @@ ProgramProcessorRegister (
case MemoryMapped:
AcquireSpinLock (&CpuFeaturesData->MemoryMappedLock);
MmioBitFieldWrite32 (
- RegisterTableEntry->Index,
+ (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
(UINT32)RegisterTableEntry->Value
diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
index 32189cb..3fec2e6 100644
--- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
+++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c
@@ -551,6 +551,7 @@ CpuRegisterTableWriteWorker (
RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry;
RegisterTableEntry[RegisterTable->TableLength].RegisterType = RegisterType;
RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32) Index;
+ RegisterTableEntry[RegisterTable->TableLength].HighIndex = (UINT32) RShiftU64 (Index, 32);
RegisterTableEntry[RegisterTable->TableLength].ValidBitStart = ValidBitStart;
RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength;
RegisterTableEntry[RegisterTable->TableLength].Value = Value;
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
index c3280b8..9404501 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c
@@ -315,7 +315,7 @@ SetProcessorRegister (
case MemoryMapped:
AcquireSpinLock (mMemoryMappedLock);
MmioBitFieldWrite32 (
- RegisterTableEntry->Index,
+ (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)),
RegisterTableEntry->ValidBitStart,
RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1,
(UINT32)RegisterTableEntry->Value
--
2.9.3.windows.2
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table
2017-03-23 5:27 [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table Jeff Fan
2017-03-23 5:27 ` [PATCH 1/2] UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64 Jeff Fan
2017-03-23 5:27 ` [PATCH 2/2] UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address Jeff Fan
@ 2017-03-27 5:30 ` Tian, Feng
2 siblings, 0 replies; 4+ messages in thread
From: Tian, Feng @ 2017-03-27 5:30 UTC (permalink / raw)
To: Fan, Jeff, edk2-devel@lists.01.org; +Cc: Tian, Feng
Series Reviewed-by: Feng Tian <feng.tian@Intel.com>
Thanks
Feng
-----Original Message-----
From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Fan, Jeff
Sent: Thursday, March 23, 2017 1:28 PM
To: edk2-devel@lists.01.org
Subject: [edk2] [PATCH 0/2] [UefiCpuPkg] Support 64bit MMIO address in CPU Register Table
The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 type actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB.
https://bugzilla.tianocore.org/show_bug.cgi?id=347
Jeff Fan (2):
UefiCpuPkg/RegisterCpuFeaturesLib: Define Index to UINT64
UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address
UefiCpuPkg/Include/AcpiCpuData.h | 12 +++++++-----
UefiCpuPkg/Include/Library/RegisterCpuFeaturesLib.h | 4 ++--
.../Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 6 +++---
.../Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 9 +++++----
UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 2 +-
5 files changed, 18 insertions(+), 15 deletions(-)
--
2.9.3.windows.2
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