From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id CE97C80473 for ; Wed, 22 Mar 2017 22:27:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=intel.com; i=@intel.com; q=dns/txt; s=intel; t=1490246868; x=1521782868; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=HSYN24j4c1WMreEJwDdtMoXPOkb9tBd+KypNZjFnzlk=; b=Owkk17pBjybcnSTuWnO5v9b/XGBwfd1eJh41m2+aOyqAJnQnyeIoFWT0 Rswqt4Ti9FyusmrkWSFzEfaOMtfbEA==; Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Mar 2017 22:27:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,208,1486454400"; d="scan'208";a="1126061582" Received: from jfan12-desk.ccr.corp.intel.com ([10.239.158.57]) by fmsmga001.fm.intel.com with ESMTP; 22 Mar 2017 22:27:47 -0700 From: Jeff Fan To: edk2-devel@lists.01.org Cc: Feng Tian , Michael Kinney Date: Thu, 23 Mar 2017 13:27:38 +0800 Message-Id: <20170323052738.10888-3-jeff.fan@intel.com> X-Mailer: git-send-email 2.9.3.windows.2 In-Reply-To: <20170323052738.10888-1-jeff.fan@intel.com> References: <20170323052738.10888-1-jeff.fan@intel.com> Subject: [PATCH 2/2] UefiCpuPkg/AcpiCpuData.h: Support >4GB MMIO address X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 23 Mar 2017 05:27:49 -0000 The current CPU_REGISTER_TABLE_ENTRY structure only defined UINT32 Index to indicate MSR/MMIO address. It's ok for MSR because MSR address is UINT32 type actually. But for MMIO address, UINT32 limits MMIO address exceeds 4GB. This update on CPU_REGISTER_TABLE_ENTRY is to add additional UINT32 field HighIndex to indicate the high 32bit MMIO address and original Index still indicate the low 32bit MMIO address. This update makes use of original padding space between ValidBitLength and Value to add HighIndex. Cc: Feng Tian Cc: Michael Kinney Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan --- UefiCpuPkg/Include/AcpiCpuData.h | 12 +++++++----- .../Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c | 6 +++--- .../Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c | 1 + UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c | 2 +- 4 files changed, 12 insertions(+), 9 deletions(-) diff --git a/UefiCpuPkg/Include/AcpiCpuData.h b/UefiCpuPkg/Include/AcpiCpuData.h index 130eb90..ec09207 100644 --- a/UefiCpuPkg/Include/AcpiCpuData.h +++ b/UefiCpuPkg/Include/AcpiCpuData.h @@ -29,11 +29,13 @@ typedef enum { // Element of register table entry // typedef struct { - REGISTER_TYPE RegisterType; - UINT32 Index; - UINT8 ValidBitStart; - UINT8 ValidBitLength; - UINT64 Value; + REGISTER_TYPE RegisterType; // offset 0 - 3 + UINT32 Index; // offset 4 - 7 + UINT8 ValidBitStart; // offset 8 + UINT8 ValidBitLength; // offset 9 + UINT16 Reserved; // offset 10 - 11 + UINT32 HighIndex; // offset 12-15, only valid for MemoryMapped + UINT64 Value; // offset 16-23 } CPU_REGISTER_TABLE_ENTRY; // diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c index d879591..34e6c6b 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/CpuFeaturesInitialize.c @@ -370,9 +370,9 @@ DumpRegisterTableOnProcessor ( case MemoryMapped: DEBUG (( DebugPrintErrorLevel, - "Processor: %d: MMIO: %x, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", + "Processor: %d: MMIO: %lx, Bit Start: %d, Bit Length: %d, Value: %lx\r\n", ProcessorNumber, - RegisterTableEntry->Index, + RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32), RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitLength, RegisterTableEntry->Value @@ -628,7 +628,7 @@ ProgramProcessorRegister ( case MemoryMapped: AcquireSpinLock (&CpuFeaturesData->MemoryMappedLock); MmioBitFieldWrite32 ( - RegisterTableEntry->Index, + (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)), RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, (UINT32)RegisterTableEntry->Value diff --git a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c index 32189cb..3fec2e6 100644 --- a/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/RegisterCpuFeaturesLib/RegisterCpuFeaturesLib.c @@ -551,6 +551,7 @@ CpuRegisterTableWriteWorker ( RegisterTableEntry = (CPU_REGISTER_TABLE_ENTRY *) (UINTN) RegisterTable->RegisterTableEntry; RegisterTableEntry[RegisterTable->TableLength].RegisterType = RegisterType; RegisterTableEntry[RegisterTable->TableLength].Index = (UINT32) Index; + RegisterTableEntry[RegisterTable->TableLength].HighIndex = (UINT32) RShiftU64 (Index, 32); RegisterTableEntry[RegisterTable->TableLength].ValidBitStart = ValidBitStart; RegisterTableEntry[RegisterTable->TableLength].ValidBitLength = ValidBitLength; RegisterTableEntry[RegisterTable->TableLength].Value = Value; diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c index c3280b8..9404501 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/CpuS3.c @@ -315,7 +315,7 @@ SetProcessorRegister ( case MemoryMapped: AcquireSpinLock (mMemoryMappedLock); MmioBitFieldWrite32 ( - RegisterTableEntry->Index, + (UINTN)(RegisterTableEntry->Index | LShiftU64 (RegisterTableEntry->HighIndex, 32)), RegisterTableEntry->ValidBitStart, RegisterTableEntry->ValidBitStart + RegisterTableEntry->ValidBitLength - 1, (UINT32)RegisterTableEntry->Value -- 2.9.3.windows.2