From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22d.google.com (mail-wr0-x22d.google.com [IPv6:2a00:1450:400c:c0c::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B20E221A04811 for ; Thu, 6 Apr 2017 02:37:46 -0700 (PDT) Received: by mail-wr0-x22d.google.com with SMTP id t20so52480131wra.1 for ; Thu, 06 Apr 2017 02:37:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=C/M0QF8K0wzU/kXbwqWWEcfMgMf/L7A/DO6TDpEFl+o=; b=VE2h1uyvrOdd9VFA5BonZ1QR8BR6/bZdNjbQ2o34GKDLUOEgZdOttyXRmliOmHenzw NHL5x49Gk52M2jz7I9bppaCQVFj17wX5zgtf0NHjRzuOBGiyTdWQn9iIK6I5L17WLVmI 4eTmcUmZAQY3CytGgjUUaT5RQyqUy1WWCV7Vg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=C/M0QF8K0wzU/kXbwqWWEcfMgMf/L7A/DO6TDpEFl+o=; b=Kb1khs16n+qkXwhRqWtGfhSSUE9FV/G12EFQVzGNDHJyg2sXTQKKXwD7NSrA5S4xxw 4AVzzedreM78kLPZF1XaQgDV9ZM9nJ8oBshRechuU6mypBwD1y5nYOZA9Mui7kpH+1xn YeozyUIUY0WFj5GPE2veaqxPs5L1yb7DjucVXX3C2R2Y/d9Y+yDu1ToicD8MfGHl5Qnr jZyNssH9AsXEacTON1J6GeTk66ps3iFa4lOELiXdZMGWwI6lFg+g3b+zvESB+Ha+IASR jDcvuurKGoepHKK8RRVRMk6EBYk/lZTHWQoc2rMP5zHBTGd5CuN8jaijmqvKr7HPo9zF qLAg== X-Gm-Message-State: AFeK/H3PL/aBIAIkJvmgNBWfJiwjNiiaFPPXoD9TCaOKSYDsEiDs2eHR6CHW1TajNVGtz21k X-Received: by 10.223.171.131 with SMTP id s3mr30841833wrc.102.1491471465066; Thu, 06 Apr 2017 02:37:45 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id o66sm1691340wmg.33.2017.04.06.02.37.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 02:37:44 -0700 (PDT) Date: Thu, 6 Apr 2017 10:37:42 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, jeremy.linton@arm.com, Evan Lloyd , Ryan Harkin Message-ID: <20170406093742.GS25239@bivouac.eciton.net> References: <1491424713-5203-1-git-send-email-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <1491424713-5203-1-git-send-email-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH 1/2] ArmPlatformPkg/HdLcdArmVExpressLib: use write-combine mapping for VRAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 09:37:47 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Apr 05, 2017 at 09:38:32PM +0100, Ard Biesheuvel wrote: > Replace the uncached memory mapping of the framebuffer with a write- > combining one. This improves performance, and avoids issues with > unaligned accesses and DC ZVA instructions performed by the accelerated > memcpy/memset routines. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel If you can get a nod each from Ryan and Evan, for the series: Reviewed-by: Leif Lindholm > --- > ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c > index a57846715ed7..d6d47545c824 100644 > --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c > +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c > @@ -143,7 +143,7 @@ LcdPlatformGetVram ( > ASSERT_EFI_ERROR(Status); > > // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable. > - Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); > + Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_WC); > ASSERT_EFI_ERROR(Status); > if (EFI_ERROR(Status)) { > gBS->FreePool (VramBaseAddress); > -- > 2.7.4 >