From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 35E7121A18AA9 for ; Thu, 6 Apr 2017 06:16:09 -0700 (PDT) Received: by mail-wm0-x22a.google.com with SMTP id t189so8825499wmt.1 for ; Thu, 06 Apr 2017 06:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=yntV8JR7Qedy6lfVbKLklwBn0TCaGGzxSRflo1jlGUc=; b=QHyFyoYYE/pyJrl7DLE1JpsHTyaaHV31fQV8j0zi359NZcgyb2+eG9SS837lfblHOq yUPXp8Dp/CQXyOApDdmD5jBWUcW3V9MHrLEn49fh3XoHGYYviMN4RxVArxlSVDvVaP3i q/yBOOyFhmkYYSyjkLOrZVPc8hem36O+Uq/CU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=yntV8JR7Qedy6lfVbKLklwBn0TCaGGzxSRflo1jlGUc=; b=p8dgZ7UCtpiNhwuqTx0sxwDoz7M25lLGY0nV//EDug1VekoU4U8GhEQO62r8KO3HvK czm1sN5WIIna1Fai2bJHiT0WGSNTYXww3A/49LQx6cym2UcYT7Jp7D8w+zmwNTO3ghu2 VxjKRTxxfZFlNT4gYUHkZIaY2oZZtdabunU22YWVGp2M6nu6EmUKItLe/oY5Z+jDSTk/ ZiFom/7Zl5xKNBNmq0pigSYNq6TYWAKWeO5ItIuwMoL3YnOQV0YI45wcvAqLM+fBYFYU YIH194cEONjtFf8iMeJrmGYgkG/bTBHfLttiYomSnh+Ls1FkPPDURmqdfGLr8oZ5Nxj1 CkBQ== X-Gm-Message-State: AFeK/H3l/E92neJ41PuIkLjazHQq/FNN9diE+DrvbRVPSdgi2/JxGPc85Bf2kuDL+quJ7KjC X-Received: by 10.28.220.212 with SMTP id t203mr24693383wmg.62.1491484567771; Thu, 06 Apr 2017 06:16:07 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id c8sm2087660wrd.57.2017.04.06.06.16.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:07 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, ryan.harkin@linaro.org, evan.lloyd@arm.com, jeremy.linton@arm.com Cc: Ard Biesheuvel Date: Thu, 6 Apr 2017 14:15:47 +0100 Message-Id: <20170406131551.3322-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170406131551.3322-1-ard.biesheuvel@linaro.org> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> Subject: [PATCH v2 1/5] ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 13:16:09 -0000 The VRAM of the PL111 on the FVP Base/Foundation models is described as device memory rather than uncached memory, which is not an accurate description of the nature of the region (i.e., a framebuffer), and may result in problems when using accelerated string routines to access the region, since this may legally involve unaligned accesses or DC ZVA instructions, which are not allowed on device mappings. So split of the 8 MB VRAM region into a separate region, and map it using memory attributes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 10 ++++++---- ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 8 +++++++- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h index 06414e6e7208..4e17c800a34f 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h @@ -40,9 +40,11 @@ #define ARM_VE_SMB_SRAM_BASE 0x2E000000 #define ARM_VE_SMB_SRAM_SZ SIZE_64KB // USB, Ethernet, VRAM -#define ARM_VE_SMB_PERIPH_BASE 0x18000000 -#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE -#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB +#define ARM_VE_SMB_PERIPH_BASE 0x18800000 +#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB) + +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000 +#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE SIZE_8MB // DRAM #define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase) @@ -75,6 +77,6 @@ #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1 // VRAM offset for the PL111 Colour LCD Controller on the motherboard -#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000) +#define VRAM_MOTHERBOARD_BASE (PL111_CLCD_VRAM_MOTHERBOARD_BASE) #endif diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c index 14c7e8e1d672..70c17ae70478 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c @@ -21,7 +21,7 @@ #include // Number of Virtual Memory Map Descriptors -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8 +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 // DDR attributes #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK @@ -130,6 +130,12 @@ ArmPlatformGetVirtualMemoryMap ( VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; + // VRAM + VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; + VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; + VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE; + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; + // Map sparse memory region if present if (HasSparseMemory) { VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase; -- 2.9.3