From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x231.google.com (mail-wm0-x231.google.com [IPv6:2a00:1450:400c:c09::231]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BE74820D77DD1 for ; Thu, 6 Apr 2017 06:16:15 -0700 (PDT) Received: by mail-wm0-x231.google.com with SMTP id o81so45328612wmb.1 for ; Thu, 06 Apr 2017 06:16:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=JzjCA8YmvF/IBZAkTgf5WNcTCS+T1mp3sZ6R3pHEtWk=; b=akbzG64AhUVt2yBZxfgoZwb9ANUovfKwMhBXd42kVBpJO6l97BZKbAhyhzKaTuQy2+ OXrGg0I5UAC7L6m1JIH/rwlJEA4RrIuic3m1lEMcCG+dIhWCzDDTH0DoU8aK32Tug71c waT1pRo10mChI3ezScmjESYKt9nhHzP6t7kbM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=JzjCA8YmvF/IBZAkTgf5WNcTCS+T1mp3sZ6R3pHEtWk=; b=JSp+c/aS66MZK099C73YPN8UKO3NdP4HXIPqd7ZhMtI/YObmNatnGvNqfuQfRz0apc pW/tUxLWGvMohHlE83HkbfF8wckN2NAHTlRQ5Faq5rdM4ary6uP5EuyRnybFFfrPX8+E vuplODqZaNnlxoKn1/Gy080KIfuQINd+9QXl3hOAv2ALQ63LPCoyVOwXU2NBYTb4C9Ib du2eCL4lH+Ony0DxfCsK8K6Ayw7Up/mmWw7N6Hvm6rWm9qaAuFUlSCMyhyjOcKVO2If3 Zb6fIgAiJYUwDInToGzqblFq5GMAuwR/x2+xbSSoJbk2TtHlnmjMNstDWdiSC+CgxoH4 iQgw== X-Gm-Message-State: AFeK/H1vQ/dDeJzyRBPOTYIVBntRb9ZaGFvr+DIo36BG7H/6k2llwHJRx6/hdoW5WB0l8FOb X-Received: by 10.28.69.68 with SMTP id s65mr24652240wma.13.1491484574333; Thu, 06 Apr 2017 06:16:14 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id c8sm2087660wrd.57.2017.04.06.06.16.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:13 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, ryan.harkin@linaro.org, evan.lloyd@arm.com, jeremy.linton@arm.com Cc: Ard Biesheuvel Date: Thu, 6 Apr 2017 14:15:50 +0100 Message-Id: <20170406131551.3322-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170406131551.3322-1-ard.biesheuvel@linaro.org> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> Subject: [PATCH v2 4/5] ArmPlatformPkg/HdLcdArmVExpressLib: use write-combine mapping for VRAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 13:16:16 -0000 Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Instead of manipulating the memory attributes directly, use the SetMemorySpaceAttributes() DXE services, which validates the attributes against the capabilities of the region before making the actual change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c | 12 ++++-------- ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf | 3 ++- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c index 67b2f14beee3..b1106ee19b98 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpress.c @@ -18,11 +18,11 @@ #include #include #include +#include #include #include #include -#include #include #include @@ -119,7 +119,6 @@ LcdPlatformGetVram ( ) { EFI_STATUS Status; - EFI_CPU_ARCH_PROTOCOL *Cpu; EFI_ALLOCATE_TYPE AllocationType; // Set the vram size @@ -138,12 +137,9 @@ LcdPlatformGetVram ( return Status; } - // Ensure the Cpu architectural protocol is already installed - Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); - ASSERT_EFI_ERROR(Status); - - // Mark the VRAM as un-cacheable. The VRAM is inside the DRAM, which is cacheable. - Status = Cpu->SetMemoryAttributes (Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable. + Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, + EFI_MEMORY_WC); ASSERT_EFI_ERROR(Status); if (EFI_ERROR(Status)) { gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES (*VramSize)); diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf index 780724737929..dff17e86fd3e 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf @@ -32,8 +32,9 @@ [Packages] ArmPlatformPkg/ArmVExpressPkg/ArmVExpressPkg.dec [LibraryClasses] - BaseLib ArmPlatformSysConfigLib + BaseLib + DxeServicesTableLib [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced -- 2.9.3