From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x236.google.com (mail-wm0-x236.google.com [IPv6:2a00:1450:400c:c09::236]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 07C1620D77DD6 for ; Thu, 6 Apr 2017 06:16:18 -0700 (PDT) Received: by mail-wm0-x236.google.com with SMTP id o81so45329564wmb.1 for ; Thu, 06 Apr 2017 06:16:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Nyu5gvclC7SseCmFnQyvFoZkMEMf+RAQZpDb1gXEJgI=; b=ONZQdetIDSGH2hgP7VC1USiq4CJ+aetCqeG4ZvgTqhU05k6CU6bO8nu0ihSyc7I+d0 1+1oSnexF77knb4UrZWsT5NejtOGSe208xZHX5EI7ChXBnMAE8teQWxqTcs6lmQz/9j4 t2QTthAhaCHxIihYmrUPVueNRKE5c5DU+q5/I= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Nyu5gvclC7SseCmFnQyvFoZkMEMf+RAQZpDb1gXEJgI=; b=qq7LCNBGaTYbtpc31VDxCwvDQmiotizHJ6qkmhA0AFzLck4XB0ArwKK/hF02zFiTvX B3CdfKn0NqbKf97hwY+rZFdUKq3tdYDR9BE8Onm77VGS6twFkiCI4nb9+N4p8vtDzO6I NoCuLHTqutkB7aOlEfbTUK2TXZIV3UqsYQEopdrV8WCGfJYqnEvrb827EXRPVuIiZid+ z4STYkNNH2j60IZpSINJRpDiG8bmnetxclvITneUhpx+xpIvZsWcE02YmH3bxj63l3GU sYM7byva+/5529Kslw3UUV6GzvtGce8iC8nQbSutXV6LfMJjaZC+U0hfLHYf8NNO5Z1Z ZgQA== X-Gm-Message-State: AFeK/H15R7LDAIN804Orruf0w+lqpUvrHsu81FVXpmkkjIexoDlCi98fAtkI5j/aeHFzOJpi X-Received: by 10.28.64.135 with SMTP id n129mr18516268wma.45.1491484576376; Thu, 06 Apr 2017 06:16:16 -0700 (PDT) Received: from localhost.localdomain ([160.163.145.113]) by smtp.gmail.com with ESMTPSA id c8sm2087660wrd.57.2017.04.06.06.16.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 06:16:15 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, ryan.harkin@linaro.org, evan.lloyd@arm.com, jeremy.linton@arm.com Cc: Ard Biesheuvel Date: Thu, 6 Apr 2017 14:15:51 +0100 Message-Id: <20170406131551.3322-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170406131551.3322-1-ard.biesheuvel@linaro.org> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> Subject: [PATCH v2 5/5] ArmPlatformPkg/PL111LcdArmVExpressLib: use write-combine mapping for VRAM X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 13:16:18 -0000 Replace the uncached memory mapping of the framebuffer with a write- combining one. This improves performance, and avoids issues with unaligned accesses and DC ZVA instructions performed by the accelerated memcpy/memset routines. Instead of manipulating the memory attributes directly, use the SetMemorySpaceAttributes() DXE services, which validates the attributes against the capabilities of the region before making the actual change. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c | 12 ++++-------- ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf | 3 ++- 2 files changed, 6 insertions(+), 9 deletions(-) diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c index a8125e81daac..3f3ceb3d2fa8 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpress.c @@ -17,10 +17,10 @@ #include #include #include +#include #include #include -#include #include #include @@ -165,7 +165,6 @@ LcdPlatformGetVram ( ) { EFI_STATUS Status; - EFI_CPU_ARCH_PROTOCOL *Cpu; Status = EFI_SUCCESS; @@ -187,12 +186,9 @@ LcdPlatformGetVram ( return Status; } - // Ensure the Cpu architectural protocol is already installed - Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); - ASSERT_EFI_ERROR(Status); - - // Mark the VRAM as un-cachable. The VRAM is inside the DRAM, which is cachable. - Status = Cpu->SetMemoryAttributes(Cpu, *VramBaseAddress, *VramSize, EFI_MEMORY_UC); + // Mark the VRAM as write-combining. The VRAM is inside the DRAM, which is cacheable. + Status = gDS->SetMemorySpaceAttributes (*VramBaseAddress, *VramSize, + EFI_MEMORY_WC); ASSERT_EFI_ERROR(Status); if (EFI_ERROR(Status)) { gBS->FreePages (*VramBaseAddress, EFI_SIZE_TO_PAGES(*VramSize)); diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf index d1978e7110d5..658558ab1523 100644 --- a/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf @@ -31,8 +31,9 @@ [Packages] ArmPlatformPkg/ArmPlatformPkg.dec [LibraryClasses] - BaseLib ArmPlatformSysConfigLib + BaseLib + DxeServicesTableLib [Protocols] gEfiEdidDiscoveredProtocolGuid # Produced -- 2.9.3