From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22a.google.com (mail-wr0-x22a.google.com [IPv6:2a00:1450:400c:c0c::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 2172121DFA903 for ; Thu, 6 Apr 2017 11:26:53 -0700 (PDT) Received: by mail-wr0-x22a.google.com with SMTP id g19so31472529wrb.0 for ; Thu, 06 Apr 2017 11:26:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=KGhxiEEMvuX2+ybFh/VesVpTzf/jD4Fo1z5vsDCejwY=; b=Zy/VPBlqqcfyy1MZ3Bbnwmv0tQINdyS2EzjVZxXZlJ6BvW4nTKV7UcI0SQKTd5tDFL WWU2d7WL/lEBBP9wZWqwQVjf0ofdblJJ8kQljTK/+57mPpfirSD40T3A2Sne5zoq3aFY qJ0pLcOGhp6Cd1T4gOobqsYNtYU6yD4XQntP0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=KGhxiEEMvuX2+ybFh/VesVpTzf/jD4Fo1z5vsDCejwY=; b=tRCprX61yVUJHz2sF6kkKW3A3Khp7kYRUbzp83wqjx3FwInMpVJ/SewkX/xAvW7RvP tp3rNH0S/tuvW0w0BSuFC2wfe0YQbRfwyalXzaIGAJTzJAtfFj4btuHfFz1emLV7JYGL CP0R1Vi5rFvn7LvqJUF9zihJNsqNHJAPfOUz2RZ/fPlW0g7WiA1DYf5krJ+whhptbVty vSR/Wh69lIFyjdtdi6KwhkDZieTj+Bai/uw+BI2q7bNuTG4IBCKK9pyU6rvHQcLTw9YX 58MtKTWJ1hiOkXzWnyQQh07xMtTdJooyjnXOXrdJgvKL3oySSdHnkRjCE/0yPeu4jy31 3tYg== X-Gm-Message-State: AFeK/H1eMWOI539TamsfkI/WB54MeUf13YP3ZTPdCvcW2QaEhSeuwa9WeseStr0vWuLgeVzW X-Received: by 10.223.150.19 with SMTP id b19mr11724090wra.98.1491503211452; Thu, 06 Apr 2017 11:26:51 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id c18sm3028943wre.48.2017.04.06.11.26.50 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 11:26:50 -0700 (PDT) Date: Thu, 6 Apr 2017 19:26:48 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, ryan.harkin@linaro.org, evan.lloyd@arm.com, jeremy.linton@arm.com Message-ID: <20170406182648.GK25239@bivouac.eciton.net> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> <20170406131551.3322-2-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20170406131551.3322-2-ard.biesheuvel@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v2 1/5] ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 18:26:53 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Apr 06, 2017 at 02:15:47PM +0100, Ard Biesheuvel wrote: > The VRAM of the PL111 on the FVP Base/Foundation models is described as > device memory rather than uncached memory, which is not an accurate > description of the nature of the region (i.e., a framebuffer), and may > result in problems when using accelerated string routines to access the > region, since this may legally involve unaligned accesses or DC ZVA > instructions, which are not allowed on device mappings. > > So split of the 8 MB VRAM region into a separate region, and map it using > memory attributes. "Normal memory attributes"? > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > --- > ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 10 ++++++---- > ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 8 +++++++- > 2 files changed, 13 insertions(+), 5 deletions(-) > > diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > index 06414e6e7208..4e17c800a34f 100644 > --- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > @@ -40,9 +40,11 @@ > #define ARM_VE_SMB_SRAM_BASE 0x2E000000 > #define ARM_VE_SMB_SRAM_SZ SIZE_64KB > // USB, Ethernet, VRAM > -#define ARM_VE_SMB_PERIPH_BASE 0x18000000 > -#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE > -#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB > +#define ARM_VE_SMB_PERIPH_BASE 0x18800000 > +#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB) > + > +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000 > +#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE SIZE_8MB > > // DRAM > #define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase) > @@ -75,6 +77,6 @@ > #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1 > > // VRAM offset for the PL111 Colour LCD Controller on the motherboard > -#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000) > +#define VRAM_MOTHERBOARD_BASE (PL111_CLCD_VRAM_MOTHERBOARD_BASE) > > #endif > diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > index 14c7e8e1d672..70c17ae70478 100644 > --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > @@ -21,7 +21,7 @@ > #include > > // Number of Virtual Memory Map Descriptors > -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8 > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 > > // DDR attributes > #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK > @@ -130,6 +130,12 @@ ArmPlatformGetVirtualMemoryMap ( > VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; > VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > > + // VRAM > + VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; > + VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; > + VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE; > + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; Hmm, looking at this made me a bit confused though. Normal uncached memory is certainly bufferable (that's basically what write-combining means). This looks like a naming hangover from ARMv5 translation table format. Is it about time we clean this up? Or have I sprained my brain? / Leif > + > // Map sparse memory region if present > if (HasSparseMemory) { > VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase; > -- > 2.9.3 >