From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x233.google.com (mail-wr0-x233.google.com [IPv6:2a00:1450:400c:c0c::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 882BA21DFA8F2 for ; Thu, 6 Apr 2017 11:45:11 -0700 (PDT) Received: by mail-wr0-x233.google.com with SMTP id c55so2415553wrc.3 for ; Thu, 06 Apr 2017 11:45:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=1p9RYnY9Vb57n8QmAU4UWkTJOgGrMUTE6Xu9cMMfhbk=; b=JTWb/sTtrrJAjDL+mnkScUl6mlVkeM1qOZjb875i+YF9WJwzNMn6XGgzGwb2XCo5Tk SFyAII3nUFRrcdvd6FYGVrFX9HBh9zfZpys6JM9WB6KKPWSIpsx9huTLzSkcE68Bx4tK ckbNGKTBxFRV1JMNXzCwwPG0aGom/vACMnJp4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=1p9RYnY9Vb57n8QmAU4UWkTJOgGrMUTE6Xu9cMMfhbk=; b=BQ6XlUD8txRCF6fUhEETIz+zLDKczDfVsbxJ1Q7bUMv+oR987PkVNBcbD0bTZ5RP0p pGHcE79LhXHNJ+KSu6Lml/mjlAiop2l97gqdZ23w99sfbyxTbNZl5JFiwu3maj2XDzze HD1n3lXGoHGanE/JzrYIKAk94KEA/3LCKQvM4X7j4ROnb4V7flcaX3O+GxSuIuycqOG6 vyeP6skgE4Daf1h9WmnLNR8EL7figujLmk6+q6kS88UXEbB26wcu35HtdQnHN5qB/9oF 5bU51j03/SIc60ZCyy4F0AvslRzhL8VhAyMcR9j5ZCZAm+spjO/eX0JANtoEvM5dnPlj JScg== X-Gm-Message-State: AN3rC/6eTkZFTBb/MaXlU/XNNQ2o5tzxpCIca5kK0k9uy4xSSbiBkPsf qqobkPz0tzYOEFsQ X-Received: by 10.28.22.1 with SMTP id 1mr5975289wmw.127.1491504309996; Thu, 06 Apr 2017 11:45:09 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m83sm27396625wmc.7.2017.04.06.11.45.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 06 Apr 2017 11:45:09 -0700 (PDT) Date: Thu, 6 Apr 2017 19:45:07 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Ryan Harkin , Evan Lloyd , Jeremy Linton Message-ID: <20170406184507.GO25239@bivouac.eciton.net> References: <20170406131551.3322-1-ard.biesheuvel@linaro.org> <20170406131551.3322-2-ard.biesheuvel@linaro.org> <20170406182648.GK25239@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v2 1/5] ArmPlatformPkg/FVP: map motherboard VRAM as uncached memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 06 Apr 2017 18:45:12 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Apr 06, 2017 at 07:31:13PM +0100, Ard Biesheuvel wrote: > On 6 April 2017 at 19:26, Leif Lindholm wrote: > > On Thu, Apr 06, 2017 at 02:15:47PM +0100, Ard Biesheuvel wrote: > >> The VRAM of the PL111 on the FVP Base/Foundation models is described as > >> device memory rather than uncached memory, which is not an accurate > >> description of the nature of the region (i.e., a framebuffer), and may > >> result in problems when using accelerated string routines to access the > >> region, since this may legally involve unaligned accesses or DC ZVA > >> instructions, which are not allowed on device mappings. > >> > >> So split of the 8 MB VRAM region into a separate region, and map it using > >> memory attributes. > > > > "Normal memory attributes"? > > > > OK > > >> > >> Contributed-under: TianoCore Contribution Agreement 1.0 > >> Signed-off-by: Ard Biesheuvel > >> --- > >> ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 10 ++++++---- > >> ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 8 +++++++- > >> 2 files changed, 13 insertions(+), 5 deletions(-) > >> > >> diff --git a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > >> index 06414e6e7208..4e17c800a34f 100644 > >> --- a/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > >> +++ b/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h > >> @@ -40,9 +40,11 @@ > >> #define ARM_VE_SMB_SRAM_BASE 0x2E000000 > >> #define ARM_VE_SMB_SRAM_SZ SIZE_64KB > >> // USB, Ethernet, VRAM > >> -#define ARM_VE_SMB_PERIPH_BASE 0x18000000 > >> -#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE > >> -#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB > >> +#define ARM_VE_SMB_PERIPH_BASE 0x18800000 > >> +#define ARM_VE_SMB_PERIPH_SZ (SIZE_64MB - SIZE_8MB) > >> + > >> +#define PL111_CLCD_VRAM_MOTHERBOARD_BASE 0x18000000 > >> +#define PL111_CLCD_VRAM_MOTHERBOARD_SIZE SIZE_8MB > >> > >> // DRAM > >> #define ARM_VE_DRAM_BASE PcdGet64 (PcdSystemMemoryBase) > >> @@ -75,6 +77,6 @@ > >> #define PL111_CLCD_CORE_TILE_VIDEO_MODE_OSC_ID 1 > >> > >> // VRAM offset for the PL111 Colour LCD Controller on the motherboard > >> -#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000) > >> +#define VRAM_MOTHERBOARD_BASE (PL111_CLCD_VRAM_MOTHERBOARD_BASE) > >> > >> #endif > >> diff --git a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > >> index 14c7e8e1d672..70c17ae70478 100644 > >> --- a/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > >> +++ b/ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c > >> @@ -21,7 +21,7 @@ > >> #include > >> > >> // Number of Virtual Memory Map Descriptors > >> -#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 8 > >> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 9 > >> > >> // DDR attributes > >> #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK > >> @@ -130,6 +130,12 @@ ArmPlatformGetVirtualMemoryMap ( > >> VirtualMemoryTable[Index].Length = 2 * ARM_VE_SMB_PERIPH_SZ; > >> VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; > >> > >> + // VRAM > >> + VirtualMemoryTable[++Index].PhysicalBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; > >> + VirtualMemoryTable[Index].VirtualBase = PL111_CLCD_VRAM_MOTHERBOARD_BASE; > >> + VirtualMemoryTable[Index].Length = PL111_CLCD_VRAM_MOTHERBOARD_SIZE; > >> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED; > > > > Hmm, looking at this made me a bit confused though. Normal uncached > > memory is certainly bufferable (that's basically what write-combining > > means). > > > > It maps to MAIR attribute encoding 0x44, which translates as > > Normal Memory, Outer Non-Cacheable, Inner Non-Cacheable Exactly - which is definitely "buffered". > > This looks like a naming hangover from ARMv5 translation table format. > > Is it about time we clean this up? > > The whole 'ARM_MEMORY_REGION_xxxx' intermediate namespace should be > removed, I think. That sounds like a good idea to me. There's also _NONSECURE crud in there. / Leif > > Or have I sprained my brain? > > > > / > > Leif > > > >> + > >> // Map sparse memory region if present > >> if (HasSparseMemory) { > >> VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase; > >> -- > >> 2.9.3 > >>