From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 55FD2219392E7 for ; Sun, 9 Apr 2017 19:42:50 -0700 (PDT) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga105.fm.intel.com with ESMTP; 09 Apr 2017 19:42:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.37,180,1488873600"; d="scan'208";a="86745902" Received: from zwei4-mobl.ccr.corp.intel.com ([10.239.197.222]) by fmsmga005.fm.intel.com with ESMTP; 09 Apr 2017 19:42:49 -0700 From: zwei4 To: edk2-devel@lists.01.org Date: Mon, 10 Apr 2017 10:42:42 +0800 Message-Id: <20170410024242.10040-1-david.wei@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 Subject: [Patch][edk2-platforms/devel-MinnowBoard3] Add code for IPC. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 10 Apr 2017 02:42:50 -0000 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 --- .../Common/Acpi/AcpiTablesPCAT/Platform.asl | 52 +++++++++++++++ .../PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c | 76 ++++++++++++++++++++++ .../Common/PlatformSettings/PlatformDxe/Platform.c | 76 ++++++++++++---------- 3 files changed, 170 insertions(+), 34 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl index 04ea3ad74..3a4cdd144 100644 --- a/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl +++ b/Platform/BroxtonPlatformPkg/Common/Acpi/AcpiTablesPCAT/Platform.asl @@ -663,6 +663,58 @@ Scope(\_SB) } } //Device (GPO3) + Scope (\_SB) { + Device(IPC1) + { + Name (_ADR, 0) + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + + Name (_DDN, "Intel(R) IPCI controller ") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00002000, BAR0) // IPC1 Bar, 8KB + Memory32Fixed (ReadWrite, 0x00000000, 0x00000004, MDAT) // PUnit mailbox Data + Memory32Fixed (ReadWrite, 0x00000000, 0x00000004, MINF) // PUnit mailbox Interface + Memory32Fixed (ReadWrite, 0x00000000, 0x00002000, BAR1) // SSRAM + IO (Decode16, 0x400, 0x480, 0x4, 0x80) //ACPI IO Base address + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) {40} // IPC1 IRQ + }) + + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField(^RBUF, ^BAR0._BAS, B0BA) + CreateDwordField(^RBUF, ^BAR0._LEN, B0LN) + Store(DD1A, B0BA) // D13A is the BAR high address for B0/D13/F1 + Store(DD1L, B0LN) // D13L is the BAR length for B0/D13/F1 + + CreateDwordField(^RBUF, ^MDAT._BAS, BM01) + CreateDwordField(^RBUF, ^MDAT._LEN, BML1) + CreateDwordField(^RBUF, ^MINF._BAS, BM02) + CreateDwordField(^RBUF, ^MINF._LEN, BML2) + Store(BMDA, BM01) // BMDA is the mail box data + Store(4, BML1) // Length for BMDA is 4 bytes + Store(BMIA, BM02) // BMDA is the mail box interface + Store(4, BML2) // Length for BMIA is 4 bytes + + CreateDwordField(^RBUF, ^BAR1._BAS, B1BA) + CreateDwordField(^RBUF, ^BAR1._LEN, B1LN) + Store(DD3A, B1BA) // D13A is the BAR high address for B0/D13/F3 + Store(DD3L, B1LN) // D13L is the BAR length for B0/D13/F3 + + Return (RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + + Return (0xF) + } + } + }//end scope } // end Scope(\_SB) diff --git a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c index 640900688..5695821ce 100644 --- a/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c +++ b/Platform/BroxtonPlatformPkg/Common/Library/PeiFspPolicyInitLib/PeiFspScPolicyInitLib.c @@ -396,6 +396,82 @@ PeiFspScPolicyInit ( } FspsUpd->FspsConfig.ResetWaitTimer = 300; + + // + // Configure Interrupt Polarity + // + FspsUpd->FspsConfig.IPC[0] = (UINT32) + ((V_ITSS_SB_IPC_ACTIVE_LOW << 31) + // IRQ 31 + (V_ITSS_SB_IPC_ACTIVE_LOW << 30) + // IRQ 30 + (V_ITSS_SB_IPC_ACTIVE_LOW << 29) + // IRQ 29 + (V_ITSS_SB_IPC_ACTIVE_LOW << 28) + // IRQ 28 + (V_ITSS_SB_IPC_ACTIVE_LOW << 27) + // IRQ 27 + (V_ITSS_SB_IPC_ACTIVE_LOW << 26) + // IRQ 26 + (V_ITSS_SB_IPC_ACTIVE_LOW << 25) + // IRQ 25 + (V_ITSS_SB_IPC_ACTIVE_LOW << 24) + // IRQ 24 + (V_ITSS_SB_IPC_ACTIVE_LOW << 23) + // IRQ 23 + (V_ITSS_SB_IPC_ACTIVE_LOW << 22) + // IRQ 22 + (V_ITSS_SB_IPC_ACTIVE_LOW << 21) + // IRQ 21 + (V_ITSS_SB_IPC_ACTIVE_LOW << 20) + // IRQ 20 + (V_ITSS_SB_IPC_ACTIVE_LOW << 19) + // IRQ 19 + (V_ITSS_SB_IPC_ACTIVE_LOW << 18) + // IRQ 18 + (V_ITSS_SB_IPC_ACTIVE_LOW << 17) + // IRQ 17 + (V_ITSS_SB_IPC_ACTIVE_LOW << 16) + // IRQ 16 + (V_ITSS_SB_IPC_ACTIVE_LOW << 15) + // IRQ 15 + (V_ITSS_SB_IPC_ACTIVE_LOW << 14) + // IRQ 14 + (V_ITSS_SB_IPC_ACTIVE_LOW << 13) + // IRQ 13 + (V_ITSS_SB_IPC_ACTIVE_HIGH << 12) + // IRQ 12 + (V_ITSS_SB_IPC_ACTIVE_LOW << 11) + // IRQ 11 + (V_ITSS_SB_IPC_ACTIVE_LOW << 10) + // IRQ 10 + (V_ITSS_SB_IPC_ACTIVE_LOW << 9) + // IRQ 9 + (V_ITSS_SB_IPC_ACTIVE_HIGH << 8) + // IRQ 8 + (V_ITSS_SB_IPC_ACTIVE_LOW << 7) + // IRQ 7 + (V_ITSS_SB_IPC_ACTIVE_LOW << 6) + // IRQ 6 + (V_ITSS_SB_IPC_ACTIVE_LOW << 5) + // IRQ 5 + (V_ITSS_SB_IPC_ACTIVE_LOW << 4) + // IRQ 4 + (V_ITSS_SB_IPC_ACTIVE_LOW << 3) + // IRQ 3 + (V_ITSS_SB_IPC_ACTIVE_HIGH << 2) + // IRQ 2 + (V_ITSS_SB_IPC_ACTIVE_HIGH << 1) + // IRQ 1 + (V_ITSS_SB_IPC_ACTIVE_HIGH << 0)) // IRQ 0 + ; + + FspsUpd->FspsConfig.IPC[1] = (UINT32) + ((V_ITSS_SB_IPC_ACTIVE_LOW << 31) + // IRQ 63 + (V_ITSS_SB_IPC_ACTIVE_LOW << 30) + // IRQ 62 + (V_ITSS_SB_IPC_ACTIVE_LOW << 29) + // IRQ 61 + (V_ITSS_SB_IPC_ACTIVE_LOW << 28) + // IRQ 60 + (V_ITSS_SB_IPC_ACTIVE_LOW << 27) + // IRQ 59 + (V_ITSS_SB_IPC_ACTIVE_LOW << 26) + // IRQ 58 + (V_ITSS_SB_IPC_ACTIVE_LOW << 25) + // IRQ 57 + (V_ITSS_SB_IPC_ACTIVE_LOW << 24) + // IRQ 56 + (V_ITSS_SB_IPC_ACTIVE_LOW << 23) + // IRQ 55 + (V_ITSS_SB_IPC_ACTIVE_LOW << 22) + // IRQ 54 + (V_ITSS_SB_IPC_ACTIVE_LOW << 21) + // IRQ 53 + (V_ITSS_SB_IPC_ACTIVE_LOW << 20) + // IRQ 52 + (V_ITSS_SB_IPC_ACTIVE_LOW << 19) + // IRQ 51 + (V_ITSS_SB_IPC_ACTIVE_LOW << 18) + // IRQ 50 + (V_ITSS_SB_IPC_ACTIVE_LOW << 17) + // IRQ 49 + (V_ITSS_SB_IPC_ACTIVE_LOW << 16) + // IRQ 48 + (V_ITSS_SB_IPC_ACTIVE_LOW << 15) + // IRQ 47 + (V_ITSS_SB_IPC_ACTIVE_LOW << 14) + // IRQ 46 + (V_ITSS_SB_IPC_ACTIVE_LOW << 13) + // IRQ 45 + (V_ITSS_SB_IPC_ACTIVE_LOW << 12) + // IRQ 44 + (V_ITSS_SB_IPC_ACTIVE_LOW << 11) + // IRQ 43 + (V_ITSS_SB_IPC_ACTIVE_LOW << 10) + // IRQ 42 + (V_ITSS_SB_IPC_ACTIVE_LOW << 9) + // IRQ 41 + (V_ITSS_SB_IPC_ACTIVE_LOW << 8) + // IRQ 40 + (V_ITSS_SB_IPC_ACTIVE_LOW << 7) + // IRQ 39 + (V_ITSS_SB_IPC_ACTIVE_LOW << 6) + // IRQ 38 + (V_ITSS_SB_IPC_ACTIVE_LOW << 5) + // IRQ 37 + (V_ITSS_SB_IPC_ACTIVE_LOW << 4) + // IRQ 36 + (V_ITSS_SB_IPC_ACTIVE_LOW << 3) + // IRQ 35 + (V_ITSS_SB_IPC_ACTIVE_LOW << 2) + // IRQ 34 + (V_ITSS_SB_IPC_ACTIVE_LOW << 1) + // IRQ 33 + (V_ITSS_SB_IPC_ACTIVE_LOW << 0)) // IRQ 32 + ; + FspsUpd->FspsConfig.IPC[2] = 0xFFFFFFFF; + FspsUpd->FspsConfig.IPC[3] = 0xFFFFFFFF; + // // Set GMM configuration according to setup value // diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c index 187eb2179..3d95c15a9 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformDxe/Platform.c @@ -114,42 +114,50 @@ PMCReadyToBoot ( &(GlobalNvsArea->Area->SSRAMBar0Address) ); - SideBandAndThenOr32 ( - 0xC6, - 0x0300 + 0x001C, - 0xFFFFFFFF, - (BIT1 | BIT0) - ); - - SideBandAndThenOr32 ( - 0xC6, - 0x0300 + 0x0038, - 0xFFFFFFFF, - BIT0 - ); - - // - // Switch the PMC SSRAM to ACPI mode. - // - SideBandAndThenOr32 ( - 0x95, - 0x208, - 0xFFFFFFFF, - BIT0 | B_PMC_IOSF2OCP_PCICFGCTRL3_BAR1_DISABLE3 - ); - - // - // Program PMC ACPI IRQ. - // - Data32 = SideBandRead32 (0x95, 0x204); - Data32 |= BIT1; - Data32 |= 0x00028000; - SideBandWrite32 (0x95, 0x204, Data32); - - Data32 = SideBandRead32 (0x95, 0x204); - DEBUG ((DEBUG_INFO, " PMC Interrupt value= %x \n ", Data32)); + SideBandAndThenOr32 ( + 0xC6, + 0x0300 + 0x001C, + 0xFFFFFFFF, + (BIT1 | BIT0) + ); + + SideBandAndThenOr32 ( + 0xC6, + 0x0300 + 0x0038, + 0xFFFFFFFF, + BIT0 + ); + + // + // Switch the PMC SSRAM to ACPI mode. + // + SideBandAndThenOr32 ( + 0x95, + 0x208, + 0xFFFFFFFF, + BIT0 | B_PMC_IOSF2OCP_PCICFGCTRL3_BAR1_DISABLE3 + ); + + // + // Program PMC ACPI IRQ. + // + Data32 = SideBandRead32 (0x95, 0x204); + Data32 |= BIT1; + Data32 |= 0x00028000; + SideBandWrite32 (0x95, 0x204, Data32); + + Data32 = SideBandRead32 (0x95, 0x204); + DEBUG ((DEBUG_INFO, " PMC Interrupt value= %x \n ", Data32)); } + + PciBar0RegOffset = (UINT32)MmPciAddress(0, DEFAULT_PCI_BUS_NUMBER_SC, 0, 0, 0x48); + PciBar0RegOffset = (MmioRead32(PciBar0RegOffset) & 0xFFFF7000); + GlobalNvsArea->Area->IPCBIOSMailBoxData = (UINT32)PciBar0RegOffset + 0x7000 + 0x80; + GlobalNvsArea->Area->IPCBIOSMailBoxInterface = (UINT32)PciBar0RegOffset + 0x7000 + 0x84; + DEBUG((DEBUG_INFO, " BIOS MAIL-BOX Data= %x \n ", GlobalNvsArea->Area->IPCBIOSMailBoxData)); + DEBUG((DEBUG_INFO, " BIOS MAIL-BOX Interface= %x \n ", GlobalNvsArea->Area->IPCBIOSMailBoxInterface)); + } -- 2.11.0.windows.1