From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9262921A13493 for ; Tue, 9 May 2017 02:34:12 -0700 (PDT) Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga105.jf.intel.com with ESMTP; 09 May 2017 02:34:12 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,313,1491289200"; d="scan'208";a="97503552" Received: from zwei4-mobl.ccr.corp.intel.com ([10.239.198.95]) by orsmga005.jf.intel.com with ESMTP; 09 May 2017 02:34:11 -0700 From: zwei4 To: edk2-devel@lists.01.org Date: Tue, 9 May 2017 17:34:06 +0800 Message-Id: <20170509093406.22780-1-david.wei@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 Subject: [Patch][edk2-platforms/devel-MinnowBoard3] Extend IBB region. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 May 2017 09:34:12 -0000 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: zwei4 --- Platform/BroxtonPlatformPkg/BuildBios.bat | 4 ++-- Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc | 2 +- Platform/BroxtonPlatformPkg/PlatformPkg.fdf | 6 +++--- .../ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 1556 -> 1556 bytes .../Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm | 2 +- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/Platform/BroxtonPlatformPkg/BuildBios.bat b/Platform/BroxtonPlatformPkg/BuildBios.bat index b57188d34..80de2f47b 100644 --- a/Platform/BroxtonPlatformPkg/BuildBios.bat +++ b/Platform/BroxtonPlatformPkg/BuildBios.bat @@ -410,9 +410,9 @@ copy /y/b %BUILD_PATH%\FV\FvOBBY.fv %Storage_Folder% >nul if /i "%FSP_WRAPPER%" == "TRUE" ( if %Stepping%==B ( -:: 0xFEF63000 = gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase = $(CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + $(FSP_EMP_DATA_SIZE) + $(BLD_IBBM_SIZE) +:: 0xFEF7A000 = gIntelFsp2WrapperTokenSpaceGuid.PcdFlashFvFspBase = $(CAR_BASE_ADDRESS) + $(BLD_RAM_DATA_SIZE) + $(FSP_RAM_DATA_SIZE) + $(FSP_EMP_DATA_SIZE) + $(BLD_IBBM_SIZE) pushd %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin - python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f ApolloLakeFsp.fd -c m -b 0xFEF63000 -o .\ -n FSP.fd + python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py rebase -f ApolloLakeFsp.fd -c m -b 0xFEF7A000 -o .\ -n FSP.fd python %WORKSPACE%\Core\IntelFsp2Pkg\Tools\SplitFspBin.py split -f FSP.fd -o .\ -n FSP.Fv popd copy /y/b %WORKSPACE%\Silicon\BroxtonSoC\BroxtonFspPkg\ApolloLakeFspBinPkg\FspBin\FSP_T.Fv %Storage_Folder%\FSP_T.Fv diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc index ff751c164..842acf308 100644 --- a/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc +++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Defines.dsc @@ -153,7 +153,7 @@ DEFINE FSP_IBBL_SIZE = 0x2000 DEFINE BLD_IBBL_SIZE = 0x6000 DEFINE FSP_IBBM_SIZE = 0x58000 - DEFINE BLD_IBBM_SIZE = 0x1E000 + DEFINE BLD_IBBM_SIZE = 0x35000 DEFINE CAR_BASE_ADDRESS = 0xFEF00000 # @PcdTemporaryRamBase DEFINE BLD_RAM_DATA_SIZE = 0x16000 # BOOTLOADER temp memory size diff --git a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf index 3b4d9e780..7522153a3 100644 --- a/Platform/BroxtonPlatformPkg/PlatformPkg.fdf +++ b/Platform/BroxtonPlatformPkg/PlatformPkg.fdf @@ -19,10 +19,10 @@ #========================================================================================== # 3MB BIOS Layout Definition #========================================================================================== - DEFINE FLASH_BASE = 0xFFD00000 #The base address of the 3MB FLASH Device. - DEFINE FLASH_SIZE = 0x00300000 #The flash size in bytes of the 3MB FLASH Device + DEFINE FLASH_BASE = 0xFFCE9000 #The base address of the 3MB FLASH Device. + DEFINE FLASH_SIZE = 0x00317000 #The flash size in bytes of the 3MB FLASH Device DEFINE FLASH_BLOCK_SIZE = 0x1000 #The block size in bytes of the 3MB FLASH Device. - DEFINE FLASH_NUM_BLOCKS = 0x300 #The number of blocks in 3MB FLASH Device. + DEFINE FLASH_NUM_BLOCKS = 0x317 #The number of blocks in 3MB FLASH Device. !else #========================================================================================== # 5MB BIOS Layout Definition diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Bin/ResetVector.ia32.port80.raw index f1fc0417a921dee98833ff797ea1ea0c4de1e2f5..2cb2466ed5e4b31b371e2f93f472d04ca217933f 100644 GIT binary patch delta 13 UcmbQjGlge@B+~_sjnY3^0UqxJjsO4v delta 13 UcmbQjGlge@BvS(WM(Lld031pL9RL6T diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm index 28560ab89..12d274676 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Cpu/ResetVector/Vtf0/Ia32/InitNEM.asm @@ -183,7 +183,7 @@ istruc HobStruc dd 0x00100000 ; .CarSize dd 0xFFF00000 ; .IBBSource = Not used dd 0xFEF45000 ; .IBBBase = .CarBase - dd 0x00076000 ; .IBBSize = size of (FVIBBM.fv+FSP_M.fv) = BLD_IBBM_SIZE + FSP_IBBM_SIZE = 0x76000 + dd 0x0008D000 ; .IBBSize = size of (FVIBBM.fv+FSP_M.fv) = BLD_IBBM_SIZE + FSP_IBBM_SIZE = 0x8D000 dd 0xFFFFF000 ; .IBBLSource = 0x100000000 - .IBBLSize = PcdFlashFvIBBLBase dd 0xFEF40000 ; .IBBLBase = .IBBBase + .IBBSize dd 0x00001000 ; .IBBLSize = PcdFlashFvIBBLSize = FLASH_REGION_FV_IBBL_SIZE in .fdf -- 2.11.0.windows.1