From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cam-smtp0.cambridge.arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 6C43E21A16EE7 for ; Tue, 16 May 2017 03:11:02 -0700 (PDT) Received: from E111747.Emea.Arm.com (e111747.emea.arm.com [10.1.29.116]) by cam-smtp0.cambridge.arm.com (8.13.8/8.13.8) with ESMTP id v4GAAow0015526; Tue, 16 May 2017 11:10:56 +0100 From: evan.lloyd@arm.com To: edk2-devel@ml01.01.org Cc: Ard Biesheuvel , Leif Lindholm , Ryan Harkin , Matteo Carlini , nd@arm.com Date: Tue, 16 May 2017 11:10:45 +0100 Message-Id: <20170516101045.14288-3-evan.lloyd@arm.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20170516101045.14288-1-evan.lloyd@arm.com> References: <20170516101045.14288-1-evan.lloyd@arm.com> Subject: [PATCH 2/2] ArmPlatformPkg: Timer access for non-secure EL1/0 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 May 2017 10:11:02 -0000 From: Sami Mujawar According to Section 2.3.6 of the "UEFI Specification 2.6 Errata A"; the primary CPU must be configured such that 'Timer access must be provided to non-secure EL1 and EL0 by setting bits EL1PCTEN and EL1PCEN in register CNTHCTL_EL2.' This commit adds this missing set-up to the PrePi and PrePeiCore modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar Signed-off-by: Evan Lloyd --- ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c | 9 ++++++++- ArmPlatformPkg/PrePeiCore/AArch64/Helper.S | 9 ++++++++- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c b/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c index 217986107e44185c2c6e11ca8a417fad659cde2f..4da590805aaae4016952c0e5e9ce90c1897e37c4 100644 --- a/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c +++ b/ArmPlatformPkg/PrePi/AArch64/ArchPrePi.c @@ -1,6 +1,6 @@ /** @file * -* Copyright (c) 2011-2013, ARM Limited. All rights reserved. +* Copyright (c) 2011-2017, ARM Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -29,5 +29,12 @@ ArchInitialize ( if (ArmReadCurrentEL () == AARCH64_EL2) { // Trap General Exceptions. All exceptions that would be routed to EL1 are routed to EL2 ArmWriteHcr (ARM_HCR_TGE); + + /* Enable Timer access for non-secure EL1 and EL0 + The cnthctl_el2 register bits are architecturally + UNKNOWN on reset. + Disable event stream as it is not in use at this stage + */ + ArmWriteCntHctl (CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN); } } diff --git a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S b/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S index 5f35484b1259f8b85c370de2cde945db2b799c13..b4f35b7ff5d389ecf61c025f85bb6cf8fcce793d 100644 --- a/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S +++ b/ArmPlatformPkg/PrePeiCore/AArch64/Helper.S @@ -1,5 +1,5 @@ #======================================================================================== -# Copyright (c) 2011-2013, ARM Limited. All rights reserved. +# Copyright (c) 2011-2017, ARM Limited. All rights reserved. # # This program and the accompanying materials # are licensed and made available under the terms and conditions of the BSD License @@ -36,6 +36,13 @@ ASM_FUNC(SetupExceptionLevel2) msr cptr_el2, xzr // Disable copro traps to EL2 + // Enable Timer access for non-secure EL1 and EL0 + // The cnthctl_el2 register bits are architecturally + // UNKNOWN on reset. + // Disable event stream as it is not in use at this stage + mov x0, #(CNTHCTL_EL2_EL1PCTEN | CNTHCTL_EL2_EL1PCEN) + msr cnthctl_el2, x0 + ret ASM_FUNCTION_REMOVE_IF_UNREFERENCED -- Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")