From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22d.google.com (mail-wm0-x22d.google.com [IPv6:2a00:1450:400c:c09::22d]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 90C9921A16EC2 for ; Fri, 19 May 2017 03:26:26 -0700 (PDT) Received: by mail-wm0-x22d.google.com with SMTP id b84so231200877wmh.0 for ; Fri, 19 May 2017 03:26:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=9Fa/PvjLYCUlP5yXgzfnZeQabfUl+ZVgHq1EfbStsK4=; b=SL9mbMmVaTIP5QCpChgvYfKPbRvds5azTSQNoWZ7n5vBcthaUsGgFkLSsDdKl1Xj8j VDB7VAEDsUpELrSzUz9E6d13nsdT9OxG4K0bRCD8C3iNdn/ZxdZS2q7MIpPi2Lyk8Pbh v6pd2NvawQFxlDfZ8XbUX9V1FvUN+yP+XrOX4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=9Fa/PvjLYCUlP5yXgzfnZeQabfUl+ZVgHq1EfbStsK4=; b=kzYuq44oQV/l5MPRE64SCJJlBFN4tkNuDVWkjuTD1MkZ6RmfWStFcgOyYzMtbw3Yho RYVGo7Bhv5EKLWZnN90A2DHTRRs3Ks2St/r9Y28E+xVhyh9SHciw0ljUcES0uKYdCx7K snp84wYyJ1r0Z3kYjEvoh0/4QUjsAi5+VoiJbENAyfMsKTIGihZ4Ys0NWbTwfkF1LvFS rLri9AMYkagU2GUEBJNrYwlKeidxHIJDexBfaEWQjcxIUDH2Ok2TqE+NeNFMkl1VGDkg wrLy4IUR8Z7+YL+SlPhIWgRqqi8/KmHCN/ag73Ov/AFPYACn2ObISMCPTON0HFmbUt3g dLaA== X-Gm-Message-State: AODbwcBZJgX95J6cYorM3xklVqUp6CCAruZIKqPbHuxRGxWENqS4YPMw wTkoV+BbsThH28j6 X-Received: by 10.28.22.12 with SMTP id 12mr19039599wmw.97.1495189584943; Fri, 19 May 2017 03:26:24 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id u4sm9228666wmu.0.2017.05.19.03.26.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 May 2017 03:26:24 -0700 (PDT) Date: Fri, 19 May 2017 11:26:22 +0100 From: Leif Lindholm To: Sergei Temerkhanov Cc: Ard Biesheuvel , "edk2-devel@lists.01.org" Message-ID: <20170519102622.GC1657@bivouac.eciton.net> References: <1494903391-716-1-git-send-email-s.temerkhanov@gmail.com> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH] Arm: GICv3: Don't access GIC_ICDIPR for interrupts 0..31 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 19 May 2017 10:26:27 -0000 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit On Fri, May 19, 2017 at 05:37:02AM +0300, Sergei Temerkhanov wrote: > On Thu, May 18, 2017 at 7:08 PM, Ard Biesheuvel > wrote: > > On 16 May 2017 at 03:56, Sergey Temerkhanov wrote: > >> These registers are reserved for PPIs and unimplemented on > >> some architectures > >> > > > > > > What do you mean by 'architectures'? > > GIC core implementations. > > > Could you elaborate on which SoC > > needs this? > At least Cavium ThunderX/OcteonTX need it. > > The GICv3 spec says this on the subject: > > 8.9.12 GICD_IPRIORITYR, Interrupt Priority Registers, n = 0 - 254 > > "These registers are always used when affinity routing is not enabled. > When affinity routing is enabled for the Security state of an > interrupt: • GICR_IPRIORITYR is used instead of GICD_IPRIORITYR where > n = 0 to 7 (that is, for SGIs and PPIs). • GICD_IPRIORITYR is RAZ/WI > where n = 0 to 7." Since they are RAZ/WI, why is this change needed? / Leif > > > >> Signed-off-by: Sergey Temerkhanov > >> --- > >> ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- > >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> > >> diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > >> index 8af97a9..dc6b896 100644 > >> --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > >> +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > >> @@ -257,7 +257,7 @@ GicV3DxeInitialize ( > >> MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE); > >> } > >> > >> - for (Index = 0; Index < mGicNumInterrupts; Index++) { > >> + for (Index = 32; Index < mGicNumInterrupts; Index++) { > >> GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index); > >> > >> // Set Priority > >> -- > >> 2.7.4 > >> > >> _______________________________________________ > >> edk2-devel mailing list > >> edk2-devel@lists.01.org > >> https://lists.01.org/mailman/listinfo/edk2-devel