From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22e.google.com (mail-wm0-x22e.google.com [IPv6:2a00:1450:400c:c09::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 82C2021A02F4D for ; Mon, 22 May 2017 10:45:16 -0700 (PDT) Received: by mail-wm0-x22e.google.com with SMTP id e127so2770959wmg.1 for ; Mon, 22 May 2017 10:45:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=doASCOhpWTLN2O9xsZllvIVXGZgtsRHCkK+WcgEWAY0=; b=IgjawloNqpiF97XVVtYcFWMw0DYknjMa+ACPxnRREq+9PPSHcKd22+LuyrF08icWSm rVgR41FLwhpM/0C+WhLB+HMAMXdk3AVYmA1djlWt1r871bk2gzoVYacO0XkTsCiCSii/ SxThCbabRpPnSv5t2FkvnLMDUGkiKGaUWVTBU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=doASCOhpWTLN2O9xsZllvIVXGZgtsRHCkK+WcgEWAY0=; b=Mhw0KseWF/7oMdHxSlsiTO9aYyetM8UZ0hwDJ0nQL0uSRAz4h3ioGAffHVEptMSsmg Xd1jmifSQvjbLBb+/MFcJfeHYL6E6kcPNBwqWR2FYjECG7fqsIV8FLjki0J35bdwSK8K U2oSkL3dTQp+zkpJduQhrAzy2RtFhAyYgPY/Qgaxg4R3WtYNyfCEGMw0xJlot3bzTsvD 3k5/s15GkNrs1EdiMBturk5BNeybI1JUcVYaTz0r8vZnnTh3/aNcTN/Q1GhrEdo3EbCT 1RHrcp3s+9axH+MDR3y0dhWXKSOEnws8YrAozVRtDquJKA8WuSRC37x3vYC5oxDt1mQu VBlA== X-Gm-Message-State: AODbwcA/U3xUic4DqI8XCTNOBA0F7eHGVciSYytN9/HpslJYHfhp2fBs J0U30GnoLIhbrBqB X-Received: by 10.28.7.16 with SMTP id 16mr6258036wmh.16.1495475114731; Mon, 22 May 2017 10:45:14 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id y3sm23374786wmh.21.2017.05.22.10.45.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 22 May 2017 10:45:14 -0700 (PDT) Date: Mon, 22 May 2017 18:45:12 +0100 From: Leif Lindholm To: Sergei Temerkhanov Cc: Ard Biesheuvel , "edk2-devel@lists.01.org" Message-ID: <20170522174512.GK1657@bivouac.eciton.net> References: <1494903391-716-1-git-send-email-s.temerkhanov@gmail.com> <20170519102622.GC1657@bivouac.eciton.net> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH] Arm: GICv3: Don't access GIC_ICDIPR for interrupts 0..31 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 22 May 2017 17:45:16 -0000 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit On Fri, May 19, 2017 at 05:31:36PM +0300, Sergei Temerkhanov wrote: > On Fri, May 19, 2017 at 1:26 PM, Leif Lindholm wrote: > > On Fri, May 19, 2017 at 05:37:02AM +0300, Sergei Temerkhanov wrote: > >> On Thu, May 18, 2017 at 7:08 PM, Ard Biesheuvel > >> wrote: > >> > On 16 May 2017 at 03:56, Sergey Temerkhanov wrote: > >> >> These registers are reserved for PPIs and unimplemented on > >> >> some architectures > >> >> > >> > > >> > > >> > What do you mean by 'architectures'? > >> > >> GIC core implementations. > >> > >> > Could you elaborate on which SoC > >> > needs this? > >> At least Cavium ThunderX/OcteonTX need it. > >> > >> The GICv3 spec says this on the subject: > >> > >> 8.9.12 GICD_IPRIORITYR, Interrupt Priority Registers, n = 0 - 254 > >> > >> "These registers are always used when affinity routing is not enabled. > >> When affinity routing is enabled for the Security state of an > >> interrupt: • GICR_IPRIORITYR is used instead of GICD_IPRIORITYR where > >> n = 0 to 7 (that is, for SGIs and PPIs). • GICD_IPRIORITYR is RAZ/WI > >> where n = 0 to 7." > > > > Since they are RAZ/WI, why is this change needed? > > B/c for some GICv3 cores accessing these registers result in exceptions Right, so that's architecturally non-compliant. At which point, as a workaround for a hardware erratum, I think this should either be a configurable option (ArmPkg Pcd), or the code should be modified to use GICR_IPRIORITYR as the text describes (if applicable). Regards, Leif > Regards, > Sergey > > > > > / > > Leif > > > >> > > >> >> Signed-off-by: Sergey Temerkhanov > >> >> --- > >> >> ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c | 2 +- > >> >> 1 file changed, 1 insertion(+), 1 deletion(-) > >> >> > >> >> diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > >> >> index 8af97a9..dc6b896 100644 > >> >> --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > >> >> +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c > >> >> @@ -257,7 +257,7 @@ GicV3DxeInitialize ( > >> >> MmioOr32 (mGicDistributorBase + ARM_GIC_ICDDCR, ARM_GIC_ICDDCR_ARE); > >> >> } > >> >> > >> >> - for (Index = 0; Index < mGicNumInterrupts; Index++) { > >> >> + for (Index = 32; Index < mGicNumInterrupts; Index++) { > >> >> GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index); > >> >> > >> >> // Set Priority > >> >> -- > >> >> 2.7.4 > >> >> > >> >> _______________________________________________ > >> >> edk2-devel mailing list > >> >> edk2-devel@lists.01.org > >> >> https://lists.01.org/mailman/listinfo/edk2-devel