From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22f.google.com (mail-wr0-x22f.google.com [IPv6:2a00:1450:400c:c0c::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B7B6A21A09105 for ; Mon, 5 Jun 2017 10:07:44 -0700 (PDT) Received: by mail-wr0-x22f.google.com with SMTP id v104so41721827wrb.0 for ; Mon, 05 Jun 2017 10:08:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=0a/BzPcYdjYLmEn04k+XJbNBs5NBWo9EDC6xKKq2C7c=; b=MIDKBZbogJLKzHB27iqVq4vJ888s//FwMzVU6eN+AJkAV5His11h7JhZ8zKyp/fvGZ kgSHpwBl7XHf+0vQbhVsp6Dp4vecP/VHNzzQmbHdGb7KsYlkDiHUH0OqZwhQm0Ryuyxe GNRuH3hMsrCRRGsSu8s4e3F91eoVmINXstvYE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=0a/BzPcYdjYLmEn04k+XJbNBs5NBWo9EDC6xKKq2C7c=; b=VFfyAmZHzpbfTCGFtgQgYa5DYcOdLLYh0LLuD6iwUJJB91ts2O39KAo+vE1FqmF/eA 61uh4ngQBTdZw//n8qKaghdRDtYzrXoPAHHWTCfDmVQG7O5AD8GN7usVLXw/NUWwAfMc ZDXrZMZ93OcU8ogwkNSogzWLrERQq8JvPpK4xYwx0GmvptuHgZAf0ZVvmvXNzVK4OokL WIoECnqV3oy4TWfelP6z+4wfZuD3UoQMkS/xJbbkxmBdXy7C/PqtkZOrMZNv3ieG3xRi 9crIClYwh/dIfPn/2vuEnjZ5BI5DctfpS3nBP/9+Re6UNFoIYm4ACr/YPNR9J6Kfbu84 e+vw== X-Gm-Message-State: AODbwcDt33hbAEClJj4m2VWwlxtGJfBnmjceDTc3iqg8AgESzLPGGkc5 jZlfgaPLd17PHNws X-Received: by 10.223.166.231 with SMTP id t94mr15327959wrc.39.1496682528754; Mon, 05 Jun 2017 10:08:48 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id l16sm6283330wre.25.2017.06.05.10.08.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Jun 2017 10:08:48 -0700 (PDT) Date: Mon, 5 Jun 2017 18:08:46 +0100 From: Leif Lindholm To: Scott Telford Cc: edk2-devel@ml01.01.org, ard.biesheuvel@linaro.org, graeme.gregory@linaro.org, afish@apple.com, michael.d.kinney@intel.com Message-ID: <20170605170846.GS7556@bivouac.eciton.net> References: <1496659828-28702-1-git-send-email-stelford@cadence.com> <1496659828-28702-4-git-send-email-stelford@cadence.com> MIME-Version: 1.0 In-Reply-To: <1496659828-28702-4-git-send-email-stelford@cadence.com> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [staging/cadence-aarch64 PATCH v2 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Jun 2017 17:07:45 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Jun 05, 2017 at 11:50:25AM +0100, Scott Telford wrote: > Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex. > This library is derived from > Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Scott Telford > --- > .../Library/CadencePciHostBridgeLib/CdnsPci.c | 103 +++++++++++ > .../Library/CadencePciHostBridgeLib/CdnsPci.h | 85 +++++++++ > .../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 189 +++++++++++++++++++++ > .../CdnsPciHostBridgeLib.inf | 77 +++++++++ > 4 files changed, 454 insertions(+) > create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c > create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h > create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c > create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf > > diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c > new file mode 100644 > index 0000000..afab354 > --- /dev/null > +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c > @@ -0,0 +1,103 @@ > +/** @file > +* Initialize the Cadence PCIe Root complex > +* > +* Copyright (c) 2017, Cadence Design Systems. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include "CdnsPci.h" > + > +STATIC > +VOID > +CdnsPciRegInit( > + EFI_CPU_IO2_PROTOCOL *CpuIo > +) While I appreciate you breaking this out into a helper function, and that really makes the init function a lot more readable, this was not exactly what I meant. (And this helper function remains fairly impenetrable without a TRM to hand.) > +{ > + UINT32 Value; > + > + // Setup the class code as PCIe Host Bridge. > + PCIE_ROOTPORT_WRITE32 (PCIE_RP + PCIE_PCI_CLASSCODE, PCIE_BRIDGE_CLASSCODE); > + > + // Set up the BARs via the Root Port registers > + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value); > + PCIE_ROOTPORT_WRITE32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value | (1 << PCIE_RCBARPIE)); > + > + // Allow incoming writes > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR0_IB, 0x1f); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR1_IB, 0x1f); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_NO_BAR_IB, 0x1f); Can we have a descriptive #define for that 0x1f, please? To a casual observer, it looks like a 5-bit flag field, and if that is the case, then having the meaning encoded in readable language would be very helpful. If the field is just meaningful seen as a whole, then the values actually used by the code would still be useful to have desctiptive #defines for. > + > + // Set up an area for Type 0 write > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG0_ADDR0, 0x18); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG0_DESC0, PCIE_AXI_TYPE0); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG0_AXI_ADDR0, 0x14); This sequence and all the remaining ones in this function follow an identical pattern: - write an address or:d with a flag (PCI end?) - write type of region - write ACI address or:d with flag > + > + // Set up an area for Type 1 write > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG1_ADDR0, PCI_ECAM_BASE + (2*PCI_BUS_SIZE) + 0x18); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG1_DESC0, PCIE_AXI_TYPE1); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG1_AXI_ADDR0, (2*PCI_BUS_SIZE) + 0x18); And in this one, 2 * PCI_BUS_SIZE (which appears to be 1MB). And some more magic values. > + > + // Set up an area for memory write > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG2_ADDR0, PCI_MEM32_BASE + 0x18); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG2_DESC0, PCIE_AXI_MEM); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG2_AXI_ADDR0, PCI_ECAM_SIZE + 0x17); > + > + // Set up an area for IO write > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG3_ADDR0, PCI_IO_BASE + 0x18); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG3_DESC0, PCIE_AXI_IO); > + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_REG3_AXI_ADDR0, (PCI_ECAM_SIZE + PCI_MEM32_SIZE) + 0x17 ); > +} And more magic values. How about a static helper function for this pattern? STATIC VOID ConfigureArea ( IN UINT32 Register, IN UINT32 Type, IN UINT32 Address, IN UINT32 Flags, IN UINT32 AxiAddress, IN UINT32 AxiFlags ) { PCIE_ROOTPORT_WRITE32 (PCIE_AXI + Register, Address | Flags); PCIE_ROOTPORT_WRITE32 (PCIE_AXI + Register + 0x08, Type); PCIE_ROOTPORT_WRITE32 (PCIE_AXI + Register + 0x18, AxiAddress | AxiFlags); // Obviously with #defines for that 0x08 and 0x18 :) } To be called as ConfigureArea ( PCIE_AXI_REG0_ADDR0, PCIE_AXI_TYPE0, 0, // Possibly with a comment describing the significance of 0 0x18, // Or rather a descriptive define resolving to this value 0, // Possibly with a comment describing the significance of 0 0x14 // Or rather a descriptive define resolving to this value ); ? > + > +EFI_STATUS > +HWPciRbInit ( > + IN EFI_HANDLE ImageHandle, > + IN EFI_SYSTEM_TABLE *SystemTable > + ) > +{ > + UINT32 Count; > + EFI_CPU_IO2_PROTOCOL *CpuIo; > + EFI_STATUS Status; > + UINT32 Value; > + > + PCI_TRACE ("HWPciRbInit()"); > + > + PCI_TRACE ("PCIe Setting up Address Translation"); > + > + Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL, > + (VOID **)&CpuIo); > + ASSERT_EFI_ERROR (Status); > + > + // Check for link up > + for (Count = 0; Count < PCI_LINK_TIMEOUT_COUNT; Count++) { > + gBS->Stall (PCI_LINK_TIMEOUT_WAIT_US); > + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_LINK_CTRL_STATUS, Value); > + if (Value & PCIE_LINK_UP) { > + break; > + } > + } > + if (!(Value & PCIE_LINK_UP)) { > + DEBUG ((DEBUG_ERROR, "PCIe link not up: %x.\n", Value)); > + return EFI_NOT_READY; > + } > + > + // Initialise configuration registers > + CdnsPciRegInit(CpuIo); > + > + return EFI_SUCCESS; > +} > diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h > new file mode 100644 > index 0000000..7d47ed6 > --- /dev/null > +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h > @@ -0,0 +1,85 @@ > +/** @file > +* Header for Cadence PCIe Root Complex > +* > +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved. > +* Copyright (c) 2017, Cadence Design Systems. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > +#ifndef __CDNS_PCI_H__ > +#define __CDNS_PCI_H__ > + > +#include > + > +#define PCI_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress) > +#define PCI_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize) > +#define PCI_IO_BASE FixedPcdGet64 (PcdPciIoBase) > +#define PCI_IO_SIZE FixedPcdGet64 (PcdPciIoSize) > +#define PCI_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base) > +#define PCI_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size) > +#define PCI_MEM64_BASE FixedPcdGet64 (PcdPciMmio64Base) > +#define PCI_MEM64_SIZE FixedPcdGet64 (PcdPciMmio64Size) > + > +#define PCI_BUS_SIZE 0x00100000 > + > +#define PCI_LINK_TIMEOUT_WAIT_US 1000 // microseconds > +#define PCI_LINK_TIMEOUT_COUNT 1000 > + > +#define PCI_TRACE(txt) DEBUG((DEBUG_VERBOSE, "CDNS_PCI: " txt "\n")) > + > +#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); } > +#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); } > +#ifdef CDNS_B2B > +#define PCIE1_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Value); } > +#define PCIE1_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Val); } > +#endif > + > +/* > + * Bridge Internal Registers > + */ > + > +// Root Port Configuration > +#define PCIE_RP 0x00200000 > +#define PCIE_PCI_CLASSCODE 0x8 > + > +// Local Management > +#define PCIE_LM 0x00100000 > +#define PCIE_LINK_CTRL_STATUS 0x00 > +#define PCIE_RP_BAR_CONFIG 0x300 > + > +// AXI Configuration > +#define PCIE_AXI 0x00400000 > +#define PCIE_AXI_REG0_ADDR0 0x000 > +#define PCIE_AXI_REG0_DESC0 0x008 > +#define PCIE_AXI_REG0_AXI_ADDR0 0x018 > +#define PCIE_AXI_REG1_ADDR0 0x020 > +#define PCIE_AXI_REG1_DESC0 0x028 > +#define PCIE_AXI_REG1_AXI_ADDR0 0x038 > +#define PCIE_AXI_REG2_ADDR0 0x040 > +#define PCIE_AXI_REG2_DESC0 0x048 > +#define PCIE_AXI_REG2_AXI_ADDR0 0x058 > +#define PCIE_AXI_REG3_ADDR0 0x060 > +#define PCIE_AXI_REG3_DESC0 0x068 > +#define PCIE_AXI_REG3_AXI_ADDR0 0x078 > +#define PCIE_AXI_BAR0_IB 0x800 > +#define PCIE_AXI_BAR1_IB 0x808 > +#define PCIE_AXI_NO_BAR_IB 0x810 > + > +// Register values > +#define PCIE_BRIDGE_CLASSCODE 0x06040000 > +#define PCIE_LINK_UP 0x01 > +#define PCIE_RCBARPIE 0x19 > +#define PCIE_AXI_TYPE0 0x80000A > +#define PCIE_AXI_TYPE1 0x80000B > +#define PCIE_AXI_MEM 0x800002 > +#define PCIE_AXI_IO 0x800006 > + > +#endif > diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c > new file mode 100644 > index 0000000..7e37948 > --- /dev/null > +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c > @@ -0,0 +1,189 @@ > +/** @file > + PCI Host Bridge support for the Cadence PCIe Root Complex > + > + Copyright (c) 2017, Linaro Ltd. All rights reserved.
> + Copyright (c) 2017, Cadence Design Systems. All rights reserved. > + > + This program and the accompanying materials are licensed and made available > + under the terms and conditions of the BSD License which accompanies this > + distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php. > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT > + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +#include > +#include (For the record, I'm not obsessive enough that I require top-level headers to be sorted in between the subdirectories. As long as each "group" is in order, I'm happy.) / Leif > + > +#pragma pack(1) > +typedef struct { > + ACPI_HID_DEVICE_PATH AcpiDevicePath; > + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; > +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > +#pragma pack () > + > +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A03), // PCI > + 0 > + }, { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > +}; > + > +STATIC PCI_ROOT_BRIDGE mRootBridge = { > + 0, // Segment > + 0, // Supports > + 0, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { > + // Bus > + FixedPcdGet32 (PcdPciBusMin), > + FixedPcdGet32 (PcdPciBusMax) > + }, { > + // Io > + FixedPcdGet64 (PcdPciIoBase), > + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 > + }, { > + // Mem > + FixedPcdGet32 (PcdPciMmio32Base), > + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1 > + }, { > + // MemAbove4G > + FixedPcdGet64 (PcdPciMmio64Base), > + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 > + }, { > + // PMem > + MAX_UINT64, > + 0 > + }, { > + // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath > +}; > + > +/** > + Return all the root bridge instances in an array. > + > + @param Count Return the count of root bridge instances. > + > + @return All the root bridge instances in an array. > + The array should be passed into PciHostBridgeFreeRootBridges() > + when it's not used. > +**/ > +PCI_ROOT_BRIDGE * > +EFIAPI > +PciHostBridgeGetRootBridges ( > + UINTN *Count > + ) > +{ > + *Count = 1; > + > + return &mRootBridge; > +} > + > +/** > + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). > + > + @param Bridges The root bridge instances array. > + @param Count The count of the array. > +**/ > +VOID > +EFIAPI > +PciHostBridgeFreeRootBridges ( > + PCI_ROOT_BRIDGE *Bridges, > + UINTN Count > + ) > +{ > +} > + > +#ifndef MDEPKG_NDEBUG > +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { > + L"Mem", L"I/O", L"Bus" > +}; > +#endif > + > +/** > + Inform the platform that the resource conflict happens. > + > + @param HostBridgeHandle Handle of the Host Bridge. > + @param Configuration Pointer to PCI I/O and PCI memory resource > + descriptors. The Configuration contains the resources > + for all the root bridges. The resource for each root > + bridge is terminated with END descriptor and an > + additional END is appended indicating the end of the > + entire resources. The resource descriptor field > + values follow the description in > + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL > + .SubmitResources(). > +**/ > +VOID > +EFIAPI > +PciHostBridgeResourceConflict ( > + EFI_HANDLE HostBridgeHandle, > + VOID *Configuration > + ) > +{ > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; > + UINTN RootBridgeIndex; > + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n")); > + > + RootBridgeIndex = 0; > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; > + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { > + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); > + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { > + ASSERT (Descriptor->ResType < > + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) > + ); > + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", > + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], > + Descriptor->AddrLen, Descriptor->AddrRangeMax > + )); > + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { > + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", > + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, > + ((Descriptor->SpecificFlag & > + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE > + ) != 0) ? L" (Prefetchable)" : L"" > + )); > + } > + } > + // > + // Skip the END descriptor for root bridge > + // > + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( > + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 > + ); > + } > +} > diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf > new file mode 100644 > index 0000000..612fd0e > --- /dev/null > +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf > @@ -0,0 +1,77 @@ > +## @file > +# PCI Host Bridge Library instance for Cadence PCIe Root Complex > +# > +# Copyright (c) 2017, Linaro Ltd. All rights reserved.
> +# Copyright (c) 2017, Cadence Design Systems. All rights reserved. > +# > +# This program and the accompanying materials are licensed and made available > +# under the terms and conditions of the BSD License which accompanies this > +# distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > +# IMPLIED. > +# > +# > +## > + > +[Defines] > + INF_VERSION = 1.25 > + BASE_NAME = CdnsPciHostBridgeLib > + FILE_GUID = d92c722c-87f9-4988-843e-dffd6bc8c5e3 > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER > + CONSTRUCTOR = HWPciRbInit > + > +# > +# The following information is for reference only and not required by the build > +# tools. > +# > +# VALID_ARCHITECTURES = AARCH64 ARM > +# > + > +[Sources] > + CdnsPciHostBridgeLib.c > + CdnsPci.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + CadencePkg/CadenceCspPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + DevicePathLib > + IoLib > + MemoryAllocationLib > + UefiBootServicesTableLib > + > +[Pcd] > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdPciBusMin > + gArmTokenSpaceGuid.PcdPciBusMax > + gArmTokenSpaceGuid.PcdPciIoBase > + gArmTokenSpaceGuid.PcdPciIoSize > + gArmTokenSpaceGuid.PcdPciIoTranslation > + gArmTokenSpaceGuid.PcdPciMmio32Base > + gArmTokenSpaceGuid.PcdPciMmio32Size > + gArmTokenSpaceGuid.PcdPciMmio32Translation > + gArmTokenSpaceGuid.PcdPciMmio64Base > + gArmTokenSpaceGuid.PcdPciMmio64Size > + gArmTokenSpaceGuid.PcdPciMmio64Translation > + gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress > + gCadenceCspTokenSpaceGuid.PcdPcie1RootPortBaseAddress > + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress > + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize > + > +[Protocols] > + gEfiCpuIo2ProtocolGuid ## CONSUMES > + > +[Depex] > + gEfiCpuIo2ProtocolGuid > -- > 2.2.2 >