From: Leif Lindholm <leif.lindholm@linaro.org>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Scott Telford <stelford@cadence.com>,
"edk2-devel@lists.01.org" <edk2-devel@ml01.01.org>,
Graeme Gregory <graeme.gregory@linaro.org>,
"afish@apple.com" <afish@apple.com>,
"Kinney, Michael D" <michael.d.kinney@intel.com>
Subject: Re: [staging/cadence-aarch64 PATCH v2 5/6] CadencePkg: Add ACPI tables for Cadence CSP platform.
Date: Tue, 6 Jun 2017 12:11:41 +0100 [thread overview]
Message-ID: <20170606111141.GX7556@bivouac.eciton.net> (raw)
In-Reply-To: <CAKv+Gu_hvQ71nLCiwJCS_9KixNkjZqitWrQoOhJXQLHX00-6Qg@mail.gmail.com>
On Mon, Jun 05, 2017 at 03:40:17PM +0000, Ard Biesheuvel wrote:
> On 5 June 2017 at 10:50, Scott Telford <stelford@cadence.com> wrote:
> > Add ACPI tables for Cadence CSP platform configured with a single
> > Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex.
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Scott Telford <stelford@cadence.com>
> > ---
> > CadencePkg/AcpiTables/AcpiTables.inf | 49 +++++
> > CadencePkg/AcpiTables/CspPlatform.h | 46 +++++
> > CadencePkg/AcpiTables/Dsdt.asl | 338 +++++++++++++++++++++++++++++++++++
> > CadencePkg/AcpiTables/Fadt.aslc | 87 +++++++++
> > CadencePkg/AcpiTables/Gtdt.aslc | 80 +++++++++
> > CadencePkg/AcpiTables/Madt.aslc | 71 ++++++++
> > CadencePkg/AcpiTables/Mcfg.aslc | 76 ++++++++
> > CadencePkg/AcpiTables/Spcr.aslc | 89 +++++++++
> > 8 files changed, 836 insertions(+)
> > create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf
> > create mode 100644 CadencePkg/AcpiTables/CspPlatform.h
> > create mode 100644 CadencePkg/AcpiTables/Dsdt.asl
> > create mode 100644 CadencePkg/AcpiTables/Fadt.aslc
> > create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc
> > create mode 100644 CadencePkg/AcpiTables/Madt.aslc
> > create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc
> > create mode 100644 CadencePkg/AcpiTables/Spcr.aslc
> >
> > diff --git a/CadencePkg/AcpiTables/Spcr.aslc b/CadencePkg/AcpiTables/Spcr.aslc
> > new file mode 100644
> > index 0000000..6ca20e8
> > --- /dev/null
> > +++ b/CadencePkg/AcpiTables/Spcr.aslc
> > @@ -0,0 +1,89 @@
> > +/** @file
> > +* SPCR Table
> > +*
> > +* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
> > +* Copyright (c) 2016, Linaro Ltd. All rights reserved.
> > +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> > +*
> > +* This program and the accompanying materials are licensed and made available
> > +* under the terms and conditions of the BSD License which accompanies this
> > +* distribution. The full text of the license may be found at
> > +* http://opensource.org/licenses/bsd-license.php
> > +*
> > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> > +*
> > +**/
> > +
> > +#include "CspPlatform.h"
> > +#include <Library/AcpiLib.h>
> > +#include <IndustryStandard/Acpi61.h>
> > +#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
> > +
> > +/**
> > + * References:
> > + * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015
> > + **/
> > +
> > +
> > +///
> > +/// SPCR Flow Control
> > +///
> > +#define SPCR_FLOW_CONTROL_NONE 0
> > +
> > +
> > +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
> > + ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
> > + // UINT8 InterfaceType;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
>
> Please drop this table entirely if your platform has no SPCR supported UART.
This is a very good point.
Yes, for this development, not having SPCR is probably fine.
However, if you want this Cadence UART to be usable as an operating
system boot console in ACPI systems, you need to get the serial port
type added to DBG2 (which is explicitly referenced from SPCR):
https://msdn.microsoft.com/en-us/library/windows/hardware/dn639131(v=vs.85).aspx
Is this something you would be interested in doing? I could probably
dig up the required contacts if that was the case.
(You would then also need to add some matching code in
linux/drivers/tty/serial/xilinx_uartps.c, to get it autodetected by
Linux.)
/
Leif
> > + // UINT8 Reserved1[3];
> > + {
> > + EFI_ACPI_RESERVED_BYTE,
> > + EFI_ACPI_RESERVED_BYTE,
> > + EFI_ACPI_RESERVED_BYTE
> > + },
> > + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
> > + ARM_GAS32 (0xFD000000),
> > + // UINT8 InterruptType;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
> > + // UINT8 Irq;
> > + 0, // Not used on ARM
> > + // UINT32 GlobalSystemInterrupt;
> > + 0x25,
> > + // UINT8 BaudRate;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
> > + // UINT8 Parity;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
> > + // UINT8 StopBits;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
> > + // UINT8 FlowControl;
> > + SPCR_FLOW_CONTROL_NONE,
> > + // UINT8 TerminalType;
> > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
> > + // UINT8 Reserved2;
> > + EFI_ACPI_RESERVED_BYTE,
> > + // UINT16 PciDeviceId;
> > + 0xFFFF,
> > + // UINT16 PciVendorId;
> > + 0xFFFF,
> > + // UINT8 PciBusNumber;
> > + 0x00,
> > + // UINT8 PciDeviceNumber;
> > + 0x00,
> > + // UINT8 PciFunctionNumber;
> > + 0x00,
> > + // UINT32 PciFlags;
> > + 0x00000000,
> > + // UINT8 PciSegment;
> > + 0x00,
> > + // UINT32 Reserved3;
> > + EFI_ACPI_RESERVED_DWORD
> > +};
> > +
> > +//
> > +// Reference the table being generated to prevent the optimizer from removing the
> > +// data structure from the executable
> > +//
> > +VOID* CONST ReferenceAcpiTable = &Spcr;
> > --
> > 2.2.2
> >
next prev parent reply other threads:[~2017-06-06 11:10 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-05 10:50 [staging/cadence-aarch64 PATCH v2 0/6] CadencePkg: Add package for Cadence hardware IP support Scott Telford
2017-06-05 10:50 ` [staging/cadence-aarch64 PATCH v2 1/6] CadencePkg: Add libraries for Cadence CSP platform Scott Telford
2017-06-05 15:12 ` Ard Biesheuvel
2017-06-05 17:19 ` Leif Lindholm
2017-06-22 9:24 ` Scott Telford
2017-06-05 17:11 ` Leif Lindholm
2017-06-22 9:24 ` Scott Telford
2017-06-05 10:50 ` [staging/cadence-aarch64 PATCH v2 2/6] CadencePkg: Add library for Cadence UART Scott Telford
2017-06-06 10:00 ` Leif Lindholm
2017-06-05 10:50 ` [staging/cadence-aarch64 PATCH v2 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex Scott Telford
2017-06-05 15:25 ` Ard Biesheuvel
2017-06-22 9:24 ` Scott Telford
2017-06-05 17:08 ` Leif Lindholm
2017-06-05 10:50 ` [staging/cadence-aarch64 PATCH v2 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform Scott Telford
2017-06-06 10:52 ` Leif Lindholm
2017-06-22 9:24 ` Scott Telford
2017-06-05 10:50 ` [staging/cadence-aarch64 PATCH v2 5/6] CadencePkg: Add ACPI tables " Scott Telford
2017-06-05 15:40 ` Ard Biesheuvel
2017-06-06 11:11 ` Leif Lindholm [this message]
2017-06-22 9:25 ` Scott Telford
2017-06-22 9:26 ` Scott Telford
2017-06-05 10:50 ` [staging/cadence-aarch64 PATCH v2 6/6] CadencePkg: Add .dsc, .fdf and .dec files " Scott Telford
2017-06-06 11:37 ` Leif Lindholm
2017-06-22 9:26 ` Scott Telford
2017-06-29 16:15 ` Leif Lindholm
2017-07-19 16:06 ` Scott Telford
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