From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wm0-x22a.google.com (mail-wm0-x22a.google.com [IPv6:2a00:1450:400c:c09::22a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C7D8621959CAC for ; Tue, 6 Jun 2017 04:10:38 -0700 (PDT) Received: by mail-wm0-x22a.google.com with SMTP id d73so46321986wma.0 for ; Tue, 06 Jun 2017 04:11:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=gy2T16sOK2JVoFw1crE7pIJ/DASNNitBa3Ay5Z/aI0o=; b=FU87Jryer3ht3cNJxy8D59bobzlejoFyzSMqMfPOqjt5ae6VN5DPr4Ra2eSGRcdXMK 62FBCx6HopIaw2vIwhhrrOTLIly14cAReh7h/fxhsR80THS8XESLWNETZDbrlQTQBYoi 9VmvO2xucn9suG/Ynxciy4GQLGQoG8QJse3DI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=gy2T16sOK2JVoFw1crE7pIJ/DASNNitBa3Ay5Z/aI0o=; b=Csi5RUMWpvhZgy9QiP5qHbOQzaweID1G85XQP/Ue98f3k9AWNin/bL1XGRgOPiI1NV J25tX3k51hW6XrhSRaohoSvqu09Z7xRRT99BV3Aye3jxHabBPpq9smCXbCCloDHv/lP5 uAcbLiw/uXN8TlmyIy3Eq/QHTtVqOniYXSAddwieZoSDKREIvxJCpl9hmmqJ+1PjbFQS 8nA5M2pu31N54gIWLnHMvrdb4iOJ7X5K5FOZITemRzdc9hTBYTaXTHY3KB0rVBCgtjpQ lfGkuJUWW1U7om/OiLFlPjyXpYgdgSTdp1TsqyK3rAAfRKX5LPPZnReFnPtLyxE5FXvI +6bQ== X-Gm-Message-State: AODbwcAPipDvAUrbZXf0EKOiiq9VUHmQOcURObia8pEi0yvuRi+QI2K3 afg6tNT74hrdMNx3 X-Received: by 10.28.220.86 with SMTP id t83mr10704958wmg.66.1496747504238; Tue, 06 Jun 2017 04:11:44 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id p187sm17801084wmd.20.2017.06.06.04.11.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Jun 2017 04:11:43 -0700 (PDT) Date: Tue, 6 Jun 2017 12:11:41 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: Scott Telford , "edk2-devel@lists.01.org" , Graeme Gregory , "afish@apple.com" , "Kinney, Michael D" Message-ID: <20170606111141.GX7556@bivouac.eciton.net> References: <1496659828-28702-1-git-send-email-stelford@cadence.com> <1496659828-28702-6-git-send-email-stelford@cadence.com> MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [staging/cadence-aarch64 PATCH v2 5/6] CadencePkg: Add ACPI tables for Cadence CSP platform. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 06 Jun 2017 11:10:39 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Mon, Jun 05, 2017 at 03:40:17PM +0000, Ard Biesheuvel wrote: > On 5 June 2017 at 10:50, Scott Telford wrote: > > Add ACPI tables for Cadence CSP platform configured with a single > > Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex. > > > > Contributed-under: TianoCore Contribution Agreement 1.0 > > Signed-off-by: Scott Telford > > --- > > CadencePkg/AcpiTables/AcpiTables.inf | 49 +++++ > > CadencePkg/AcpiTables/CspPlatform.h | 46 +++++ > > CadencePkg/AcpiTables/Dsdt.asl | 338 +++++++++++++++++++++++++++++++++++ > > CadencePkg/AcpiTables/Fadt.aslc | 87 +++++++++ > > CadencePkg/AcpiTables/Gtdt.aslc | 80 +++++++++ > > CadencePkg/AcpiTables/Madt.aslc | 71 ++++++++ > > CadencePkg/AcpiTables/Mcfg.aslc | 76 ++++++++ > > CadencePkg/AcpiTables/Spcr.aslc | 89 +++++++++ > > 8 files changed, 836 insertions(+) > > create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf > > create mode 100644 CadencePkg/AcpiTables/CspPlatform.h > > create mode 100644 CadencePkg/AcpiTables/Dsdt.asl > > create mode 100644 CadencePkg/AcpiTables/Fadt.aslc > > create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc > > create mode 100644 CadencePkg/AcpiTables/Madt.aslc > > create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc > > create mode 100644 CadencePkg/AcpiTables/Spcr.aslc > > > > diff --git a/CadencePkg/AcpiTables/Spcr.aslc b/CadencePkg/AcpiTables/Spcr.aslc > > new file mode 100644 > > index 0000000..6ca20e8 > > --- /dev/null > > +++ b/CadencePkg/AcpiTables/Spcr.aslc > > @@ -0,0 +1,89 @@ > > +/** @file > > +* SPCR Table > > +* > > +* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved. > > +* Copyright (c) 2016, Linaro Ltd. All rights reserved. > > +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved. > > +* > > +* This program and the accompanying materials are licensed and made available > > +* under the terms and conditions of the BSD License which accompanies this > > +* distribution. The full text of the license may be found at > > +* http://opensource.org/licenses/bsd-license.php > > +* > > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > > +* > > +**/ > > + > > +#include "CspPlatform.h" > > +#include > > +#include > > +#include > > + > > +/** > > + * References: > > + * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015 > > + **/ > > + > > + > > +/// > > +/// SPCR Flow Control > > +/// > > +#define SPCR_FLOW_CONTROL_NONE 0 > > + > > + > > +STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = { > > + ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE, > > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE, > > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION), > > + // UINT8 InterfaceType; > > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART, > > Please drop this table entirely if your platform has no SPCR supported UART. This is a very good point. Yes, for this development, not having SPCR is probably fine. However, if you want this Cadence UART to be usable as an operating system boot console in ACPI systems, you need to get the serial port type added to DBG2 (which is explicitly referenced from SPCR): https://msdn.microsoft.com/en-us/library/windows/hardware/dn639131(v=vs.85).aspx Is this something you would be interested in doing? I could probably dig up the required contacts if that was the case. (You would then also need to add some matching code in linux/drivers/tty/serial/xilinx_uartps.c, to get it autodetected by Linux.) / Leif > > + // UINT8 Reserved1[3]; > > + { > > + EFI_ACPI_RESERVED_BYTE, > > + EFI_ACPI_RESERVED_BYTE, > > + EFI_ACPI_RESERVED_BYTE > > + }, > > + // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress; > > + ARM_GAS32 (0xFD000000), > > + // UINT8 InterruptType; > > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC, > > + // UINT8 Irq; > > + 0, // Not used on ARM > > + // UINT32 GlobalSystemInterrupt; > > + 0x25, > > + // UINT8 BaudRate; > > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200, > > + // UINT8 Parity; > > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY, > > + // UINT8 StopBits; > > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1, > > + // UINT8 FlowControl; > > + SPCR_FLOW_CONTROL_NONE, > > + // UINT8 TerminalType; > > + EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI, > > + // UINT8 Reserved2; > > + EFI_ACPI_RESERVED_BYTE, > > + // UINT16 PciDeviceId; > > + 0xFFFF, > > + // UINT16 PciVendorId; > > + 0xFFFF, > > + // UINT8 PciBusNumber; > > + 0x00, > > + // UINT8 PciDeviceNumber; > > + 0x00, > > + // UINT8 PciFunctionNumber; > > + 0x00, > > + // UINT32 PciFlags; > > + 0x00000000, > > + // UINT8 PciSegment; > > + 0x00, > > + // UINT32 Reserved3; > > + EFI_ACPI_RESERVED_DWORD > > +}; > > + > > +// > > +// Reference the table being generated to prevent the optimizer from removing the > > +// data structure from the executable > > +// > > +VOID* CONST ReferenceAcpiTable = &Spcr; > > -- > > 2.2.2 > >