Re: [PATCH] EmbeddedPkg/MmcDxe: Add non-DDR timing mode support

[Leif Lindholm <leif.lindholm@linaro.org>]

Hi Jun,

Don't forget to cc the package maintainers on your patch submission,
as found in top-level Maintainers.txt.

On Thu, Jun 08, 2017 at 04:12:27PM +0800, Jun Nie wrote:
> Only DDR mode is support for 8bit mode currently. Add
> non-DDR case when configuring ECSD.
> 
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
> ---
>  EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
> index 574a77e..5c0d7e7 100644
> --- a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
> +++ b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c
> @@ -286,7 +286,10 @@ InitializeEmmcDevice (
>      }
>      Status = Host->SetIos (Host, BusClockFreq, 8, TimingMode[Idx]);
>      if (!EFI_ERROR (Status)) {
> -      Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT);
> +      if (Idx < 2)

While currently programatically correct, this would break if anyone
changed the order of entries in TimingMode.

A less fragile test would be
  if (TimingMode[Idx] & (EMMCHS52DDR1V2 | EMMCHS52DDR1V8))

(If we ever need to support HS400 devices in this function, I would
suggest a rewrite without fixed indexes and with a helper macro to
determine DDR-ness.)

Regards,

Leif

> +        Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT);
> +      else
> +        Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_8BIT);
>        if (EFI_ERROR (Status)) {
>          DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus width, Status:%r\n", Status));
>        }
> -- 
> 1.9.1
> 
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