From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x229.google.com (mail-wr0-x229.google.com [IPv6:2a00:1450:400c:c0c::229]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8AA4C20082E76 for ; Thu, 8 Jun 2017 09:50:50 -0700 (PDT) Received: by mail-wr0-x229.google.com with SMTP id v111so20984741wrc.3 for ; Thu, 08 Jun 2017 09:51:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=A3ODJvugiI18378uFfgT/2fumkw/QHSPPO+giTqgvyc=; b=Svixer77DIdlDf7hBT4nivt+NK1SOgD9xpzlSraxVccHVcogY0XI07fbkEnG7q+pNq J+FblAaayiIf4jbJS13d76ShhKjvv/a0Zl5FmWoLmTamD+RyMWvKhwaSjGCQHZnYmrmH JiBuYfoOhvzDV35i+JQHqjddc/4PdwVOGPlfw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=A3ODJvugiI18378uFfgT/2fumkw/QHSPPO+giTqgvyc=; b=OQ6sQCMpMSKmugPHd/YPkYwbBsZS2V+oScvJlyZdnecu5M4CjKLIR/otjDiTWTo48b omj+krcLjQKUPe5/s2ndeOV5Qw2bNez6Jxoy2WIEG25agjqohW80+e+WqjtyVbRgtIwG OVxaVWheVxtVusufWepmbxaf4ZZ04ikGsx8ZkRqQf8+MXW1F9UPXMpqTMo7qKdWKmEYt aTWIhrCx6PkSoVoBu8unOzHHaNYNWwjJjp/k+DYsbZFpWBXc95J2f0vPFomYXsgXmtII rJ0Z6ezhjvNeGOs+keqgBA8SUxfpL7mHzj3HWVigomlV5VOjrG2PcNGV5jB8Zlr8L75G lscA== X-Gm-Message-State: AODbwcD6p1cJMY2dZ+pJfJuH7zuK8rk/woKrz8GfhgAaTiQBhMlnmkDw qARCxQyhxCc0mhTC X-Received: by 10.223.167.75 with SMTP id e11mr16469452wrd.95.1496940718358; Thu, 08 Jun 2017 09:51:58 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id z184sm965253wmz.0.2017.06.08.09.51.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 08 Jun 2017 09:51:57 -0700 (PDT) Date: Thu, 8 Jun 2017 17:51:56 +0100 From: Leif Lindholm To: Jun Nie Cc: haojian.zhuang@linaro.org, edk2-devel@lists.01.org, jason.liu@linaro.org, shawn.guo@linaro.org, ard.biesheuvel@linaro.org Message-ID: <20170608165156.GA26676@bivouac.eciton.net> References: <1496909547-16085-1-git-send-email-jun.nie@linaro.org> MIME-Version: 1.0 In-Reply-To: <1496909547-16085-1-git-send-email-jun.nie@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH] EmbeddedPkg/MmcDxe: Add non-DDR timing mode support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jun 2017 16:50:51 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Jun, Don't forget to cc the package maintainers on your patch submission, as found in top-level Maintainers.txt. On Thu, Jun 08, 2017 at 04:12:27PM +0800, Jun Nie wrote: > Only DDR mode is support for 8bit mode currently. Add > non-DDR case when configuring ECSD. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jun Nie > --- > EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c > index 574a77e..5c0d7e7 100644 > --- a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c > +++ b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c > @@ -286,7 +286,10 @@ InitializeEmmcDevice ( > } > Status = Host->SetIos (Host, BusClockFreq, 8, TimingMode[Idx]); > if (!EFI_ERROR (Status)) { > - Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT); > + if (Idx < 2) While currently programatically correct, this would break if anyone changed the order of entries in TimingMode. A less fragile test would be if (TimingMode[Idx] & (EMMCHS52DDR1V2 | EMMCHS52DDR1V8)) (If we ever need to support HS400 devices in this function, I would suggest a rewrite without fixed indexes and with a helper macro to determine DDR-ness.) Regards, Leif > + Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT); > + else > + Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_8BIT); > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus width, Status:%r\n", Status)); > } > -- > 1.9.1 > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel