From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4DB4121967BEB for ; Thu, 8 Jun 2017 10:12:30 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx02.intmail.prod.int.phx2.redhat.com [10.5.11.12]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 1362189C2A; Thu, 8 Jun 2017 17:13:39 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 1362189C2A Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx03.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 1362189C2A Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-122.phx2.redhat.com [10.3.116.122]) by smtp.corp.redhat.com (Postfix) with ESMTP id 4875F7F1C0; Thu, 8 Jun 2017 17:13:38 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Jordan Justen Date: Thu, 8 Jun 2017 19:13:30 +0200 Message-Id: <20170608171333.17937-3-lersek@redhat.com> In-Reply-To: <20170608171333.17937-1-lersek@redhat.com> References: <20170608171333.17937-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.27]); Thu, 08 Jun 2017 17:13:39 +0000 (UTC) Subject: [PATCH 2/5] OvmfPkg/PlatformPei: rebase to Q35TsegSizeLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Jun 2017 17:12:30 -0000 Replace FixedPcdGet8 (PcdQ35TsegMbytes) macro invocations with Q35TsegSizeGetPreferredMbytes () function invocations. This causes no change in observable behavior. Remember that Q35TsegSizeGetPreferredMbytes() -- indirectly -- logs an error and calls CpuDeadLoop() if it is executed on a non-Q35 board. This is safe and intentional, because all the converted call sites are reached only when the PcdSmmSmramRequire Feature PCD is set, for which Q35 has always been a hard requirement. Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/PlatformPei/PlatformPei.inf | 2 +- OvmfPkg/PlatformPei/MemDetect.c | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/PlatformPei.inf index a1e12c1fc7e2..6125b52b8466 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -57,14 +57,15 @@ [LibraryClasses] PeiServicesLib PeiServicesTablePointerLib PeimEntryPoint QemuFwCfgLib QemuFwCfgS3Lib MtrrLib PcdLib + Q35TsegSizeLib [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase @@ -78,15 +79,14 @@ [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd - gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index af96a04d194a..795a3f47d12a 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -29,14 +29,15 @@ Module Name: #include #include #include #include #include #include #include +#include #include "Platform.h" #include "Cmos.h" UINT8 mPhysMemAddressWidth; STATIC UINT32 mS3AcpiReservedMemoryBase; @@ -344,15 +345,15 @@ PublishPeiMemory ( UINT32 PeiMemoryCap; LowerMemorySize = GetSystemMemorySizeBelow4gb (); if (FeaturePcdGet (PcdSmmSmramRequire)) { // // TSEG is chipped from the end of low RAM // - LowerMemorySize -= FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + LowerMemorySize -= Q35TsegSizeGetPreferredMbytes () * SIZE_1MB; } // // If S3 is supported, then the S3 permanent PEI memory is placed next, // downwards. Its size is primarily dictated by CpuMpPei. The formula below // is an approximation. // @@ -452,15 +453,15 @@ QemuInitializeRam ( // Create memory HOBs // AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; - TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize = Q35TsegSizeGetPreferredMbytes () * SIZE_1MB; AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, TRUE); } else { AddMemoryRangeHob (BASE_1MB, LowerMemorySize); } @@ -601,15 +602,15 @@ InitializeRamRegions ( if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; // // Make sure the TSEG area that we reported as a reserved memory resource // cannot be used for reserved memory allocations. // - TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize = Q35TsegSizeGetPreferredMbytes () * SIZE_1MB; BuildMemoryAllocationHob ( GetSystemMemorySizeBelow4gb() - TsegSize, TsegSize, EfiReservedMemoryType ); } } -- 2.9.3