[PATCH 4/5] OvmfPkg/SmmAccess: rebase shared PEIM/DXE code to Q35TsegSizeLib

[Laszlo Ersek <lersek@redhat.com>]

SmmAccessPei and SmmAccess2Dxe share the internals between their
PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL implementations,
respectively, in "SmramInternal.c".

In this patch, convert "SmramInternal.c" to Q35TsegSizeLib client code.
Replace any mapping, from MCH_ESMRAMC_TSEG_xMB bitmask macros to byte
counts, with

  (Q35TsegSizeConvertEsmramcValToMbytes (EsmramcVal) * SIZE_1MB)

expressions.

This causes no change in observable behavior.

After this patch, the conversion to Q35TsegSizeLib is complete.

Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
---
 OvmfPkg/SmmAccess/SmmAccess2Dxe.inf |  1 +
 OvmfPkg/SmmAccess/SmramInternal.c   | 13 ++++++-------
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf b/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
index 31e4dfa02991..f591b837bb62 100644
--- a/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
+++ b/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf
@@ -41,14 +41,15 @@ [Packages]
   MdePkg/MdePkg.dec
   OvmfPkg/OvmfPkg.dec
 
 [LibraryClasses]
   DebugLib
   PcdLib
   PciLib
+  Q35TsegSizeLib
   UefiBootServicesTableLib
   UefiDriverEntryPoint
 
 [Protocols]
   gEfiSmmAccess2ProtocolGuid   ## PRODUCES
 
 [FeaturePcd]
diff --git a/OvmfPkg/SmmAccess/SmramInternal.c b/OvmfPkg/SmmAccess/SmramInternal.c
index c3267ca94031..e7a7acbf1f8b 100644
--- a/OvmfPkg/SmmAccess/SmramInternal.c
+++ b/OvmfPkg/SmmAccess/SmramInternal.c
@@ -14,14 +14,15 @@
 
 **/
 
 #include <Guid/AcpiS3Context.h>
 #include <IndustryStandard/Q35MchIch9.h>
 #include <Library/DebugLib.h>
 #include <Library/PciLib.h>
+#include <Library/Q35TsegSizeLib.h>
 
 #include "SmramInternal.h"
 
 /**
   Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and
   OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL object,
   from the D_LCK and T_EN bits.
@@ -128,15 +129,15 @@ SmramAccessGetCapabilities (
   IN OUT UINTN                *SmramMapSize,
   IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap
   )
 {
   UINTN  OriginalSize;
   UINT32 TsegMemoryBaseMb, TsegMemoryBase;
   UINT64 CommonRegionState;
-  UINT8  TsegSizeBits;
+  UINT8  EsmramcVal;
 
   OriginalSize  = *SmramMapSize;
   *SmramMapSize = DescIdxCount * sizeof *SmramMap;
   if (OriginalSize < *SmramMapSize) {
     return EFI_BUFFER_TOO_SMALL;
   }
 
@@ -162,27 +163,25 @@ SmramAccessGetCapabilities (
   SmramMap[DescIdxSmmS3ResumeState].CpuStart      = TsegMemoryBase;
   SmramMap[DescIdxSmmS3ResumeState].PhysicalSize  =
     EFI_PAGES_TO_SIZE (EFI_SIZE_TO_PAGES (sizeof (SMM_S3_RESUME_STATE)));
   SmramMap[DescIdxSmmS3ResumeState].RegionState   =
     CommonRegionState | EFI_ALLOCATED;
 
   //
-  // Get the TSEG size bits from the ESMRAMC register.
+  // Read the ESMRAMC register so we can extract the TSEG size bits.
   //
-  TsegSizeBits = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC)) &
-                 MCH_ESMRAMC_TSEG_MASK;
+  EsmramcVal = PciRead8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC));
 
   //
   // The second region is the main one, following the first.
   //
   SmramMap[DescIdxMain].PhysicalStart =
     SmramMap[DescIdxSmmS3ResumeState].PhysicalStart +
     SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
   SmramMap[DescIdxMain].CpuStart = SmramMap[DescIdxMain].PhysicalStart;
   SmramMap[DescIdxMain].PhysicalSize =
-    (TsegSizeBits == MCH_ESMRAMC_TSEG_8MB ? SIZE_8MB :
-     TsegSizeBits == MCH_ESMRAMC_TSEG_2MB ? SIZE_2MB :
-     SIZE_1MB) - SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
+    (Q35TsegSizeConvertEsmramcValToMbytes (EsmramcVal) * SIZE_1MB) -
+    SmramMap[DescIdxSmmS3ResumeState].PhysicalSize;
   SmramMap[DescIdxMain].RegionState = CommonRegionState;
 
   return EFI_SUCCESS;
 }
-- 
2.9.3