From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22f.google.com (mail-wr0-x22f.google.com [IPv6:2a00:1450:400c:c0c::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8CED821BB2525 for ; Mon, 12 Jun 2017 08:28:03 -0700 (PDT) Received: by mail-wr0-x22f.google.com with SMTP id v111so101493887wrc.3 for ; Mon, 12 Jun 2017 08:29:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=sz6TCQKo0ugTn5s4b5IeYKAQAyVsFPOLC+GrWzzQTDc=; b=BB2gpKM7Wbgtkl2NMrs3Wh7ab9VO0ktzvjH6CJhanriZITarPwcCLbmhiWWBrqU5gM V9m8HKJjIepn4+y+tq/MbU366DoR/w6Z2luDtZjFFm7a58wqkkNL/AcYtgx8XL8FuMha +G//J3NwrkUWefNtR8SchMPEW56yosV+lzSos= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=sz6TCQKo0ugTn5s4b5IeYKAQAyVsFPOLC+GrWzzQTDc=; b=E9l+2kU93JZVfxwC00U6wuM2VGqKOKzrSVFc3b1q2aWGKaWmQKhaYAvQy21YRRhjMn skpvEEwZ0ut2sF1mDdxVqOaUKPzwQjsfWw68dKNfZWU3DiqNZ7K9pnElVCw8YHHHETyp OAuCdrC+E63exelHrVqKH0Qs3gAOlM2/p9U2DRZ6XtHQyqnY8i4pXnnXGeo9NquPwiDU g6N1E0r63Xo3wiLvBFTY+UYX9sK/Jh4cewUOzHqsCS6GEApBDW90tMl1t0GnJzGJ7ZY+ NgdNssejo+qbARzD6ohdXuQ8SjK4m7KBdzxClRNp/h4bvUS4Gk3YFH4MArztvIXVgZAY XL1Q== X-Gm-Message-State: AKS2vOxJgw/KEUTgRfXrBSyPPtJ3gPaNHmZrjFQVO1xiDr8aaFIE25Av jr4YyD60Rs5sCsUT X-Received: by 10.28.13.1 with SMTP id 1mr8518569wmn.12.1497281354450; Mon, 12 Jun 2017 08:29:14 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id l129sm5233676wmb.17.2017.06.12.08.29.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Jun 2017 08:29:13 -0700 (PDT) Date: Mon, 12 Jun 2017 16:29:12 +0100 From: Leif Lindholm To: Jun Nie Cc: ard.biesheuvel@linaro.org, olivier.martin@arm.com, haojian.zhuang@linaro.org, edk2-devel@lists.01.org, shawn.guo@linaro.org, jason.liu@linaro.org Message-ID: <20170612152912.GJ26676@bivouac.eciton.net> References: <1497233885-11082-1-git-send-email-jun.nie@linaro.org> MIME-Version: 1.0 In-Reply-To: <1497233885-11082-1-git-send-email-jun.nie@linaro.org> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [PATCH v2] EmbeddedPkg/MmcDxe: Add non-DDR timing mode support X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 12 Jun 2017 15:28:04 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline (olivier.martin@arm.com has not been a valid email target for almost 2 years now, so no need to keep on cc.) On Mon, Jun 12, 2017 at 10:18:05AM +0800, Jun Nie wrote: > Only DDR mode is support for 8bit mode currently. Add > non-DDR case when configuring ECSD. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Jun Nie This looks good to me: Reviewed-by: Leif Lindholm > --- > EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c > index 574a77e..4ce0ddd 100644 > --- a/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c > +++ b/EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c > @@ -254,7 +254,7 @@ InitializeEmmcDevice ( > EFI_MMC_HOST_PROTOCOL *Host; > EFI_STATUS Status = EFI_SUCCESS; > ECSD *ECSDData; > - UINT32 BusClockFreq, Idx; > + UINT32 BusClockFreq, Idx, BusMode; > UINT32 TimingMode[4] = {EMMCHS52DDR1V2, EMMCHS52DDR1V8, EMMCHS52, EMMCHS26}; > > Host = MmcHostInstance->MmcHost; > @@ -286,7 +286,19 @@ InitializeEmmcDevice ( > } > Status = Host->SetIos (Host, BusClockFreq, 8, TimingMode[Idx]); > if (!EFI_ERROR (Status)) { > - Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT); > + switch (TimingMode[Idx]) { > + case EMMCHS52DDR1V2: > + case EMMCHS52DDR1V8: > + BusMode = EMMC_BUS_WIDTH_DDR_8BIT; > + break; > + case EMMCHS52: > + case EMMCHS26: > + BusMode = EMMC_BUS_WIDTH_8BIT; > + break; > + default: > + return EFI_UNSUPPORTED; > + } > + Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, BusMode); > if (EFI_ERROR (Status)) { > DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus width, Status:%r\n", Status)); > } > -- > 1.9.1 >