From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 8DF9821A00AD9 for ; Wed, 28 Jun 2017 03:38:37 -0700 (PDT) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jun 2017 03:40:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,275,1496127600"; d="scan'208";a="279555740" Received: from ray-dev.ccr.corp.intel.com ([10.239.9.28]) by fmsmga004.fm.intel.com with ESMTP; 28 Jun 2017 03:40:07 -0700 From: Ruiyu Ni To: edk2-devel@lists.01.org Cc: Hao A Wu , Star Zeng , Feng Tian Date: Wed, 28 Jun 2017 18:39:57 +0800 Message-Id: <20170628103959.397244-2-ruiyu.ni@intel.com> X-Mailer: git-send-email 2.12.2.windows.2 In-Reply-To: <20170628103959.397244-1-ruiyu.ni@intel.com> References: <20170628103959.397244-1-ruiyu.ni@intel.com> Subject: [PATCH 1/3] MdeModulePkg/XhciDxe: Refine IsTransferRingTrb and IsAsyncIntTrb X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 28 Jun 2017 10:38:37 -0000 Current implementation of IsTransferRingTrb only checks whether the TRB is in the RING of the URB. The patch enhanced the logic to check that whether the TRB belongs to the transaction of URB. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni Cc: Hao A Wu Cc: Star Zeng Cc: Feng Tian --- MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c | 93 ++++++++++++++++---------------- 1 file changed, 47 insertions(+), 46 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c index 457344051b..93803c352e 100644 --- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c +++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c @@ -977,45 +977,45 @@ XhcFreeSched ( } /** - Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list. + Check if the Trb is a transaction of the URB. - @param Xhc The XHCI Instance. - @param Trb The TRB to be checked. - @param Urb The pointer to the matched Urb. + @param Trb The TRB to be checked + @param Urb The URB to be checked. - @retval TRUE The Trb is matched with a transaction of the URBs in the async list. - @retval FALSE The Trb is not matched with any URBs in the async list. + @retval TRUE It is a transaction of the URB. + @retval FALSE It is not any transaction of the URB. **/ BOOLEAN -IsAsyncIntTrb ( +IsTransferRingTrb ( IN USB_XHCI_INSTANCE *Xhc, IN TRB_TEMPLATE *Trb, - OUT URB **Urb + IN URB *Urb ) { - LIST_ENTRY *Entry; - LIST_ENTRY *Next; - TRB_TEMPLATE *CheckedTrb; - URB *CheckedUrb; - UINTN Index; + LINK_TRB *LinkTrb; + TRB_TEMPLATE *CheckedTrb; + UINTN Index; + EFI_PHYSICAL_ADDRESS PhyAddr; - EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { - CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList); - CheckedTrb = CheckedUrb->TrbStart; - for (Index = 0; Index < CheckedUrb->TrbNum; Index++) { - if (Trb == CheckedTrb) { - *Urb = CheckedUrb; - return TRUE; - } - CheckedTrb++; - // - // If the checked TRB is the link TRB at the end of the transfer ring, - // recircle it to the head of the ring. - // - if (CheckedTrb->Type == TRB_TYPE_LINK) { - CheckedTrb = (TRB_TEMPLATE*) CheckedUrb->Ring->RingSeg0; - } + CheckedTrb = Urb->TrbStart; + if (CheckedTrb->Type == TRB_TYPE_NORMAL) { + ASSERT (Urb->TrbNum == 1); + } + for (Index = 0; Index < Urb->TrbNum; Index++) { + if (Trb == CheckedTrb) { + return TRUE; + } + CheckedTrb++; + // + // If the checked TRB is the link TRB at the end of the transfer ring, + // recircle it to the head of the ring. + // + if (CheckedTrb->Type == TRB_TYPE_LINK) { + LinkTrb = (LINK_TRB *) CheckedTrb; + PhyAddr = (EFI_PHYSICAL_ADDRESS)(LinkTrb->PtrLo | LShiftU64 ((UINT64) LinkTrb->PtrHi, 32)); + CheckedTrb = (TRB_TEMPLATE *)(UINTN) UsbHcGetHostAddrForPciAddr (Xhc->MemPool, (VOID *)(UINTN) PhyAddr, sizeof (TRB_TEMPLATE)); + ASSERT (CheckedTrb == Urb->Ring->RingSeg0); } } @@ -1023,38 +1023,39 @@ IsAsyncIntTrb ( } /** - Check if the Trb is a transaction of the URB. + Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list. - @param Trb The TRB to be checked - @param Urb The transfer ring to be checked. + @param Xhc The XHCI Instance. + @param Trb The TRB to be checked. + @param Urb The pointer to the matched Urb. - @retval TRUE It is a transaction of the URB. - @retval FALSE It is not any transaction of the URB. + @retval TRUE The Trb is matched with a transaction of the URBs in the async list. + @retval FALSE The Trb is not matched with any URBs in the async list. **/ BOOLEAN -IsTransferRingTrb ( +IsAsyncIntTrb ( + IN USB_XHCI_INSTANCE *Xhc, IN TRB_TEMPLATE *Trb, - IN URB *Urb + OUT URB **Urb ) { - TRB_TEMPLATE *CheckedTrb; - UINTN Index; - - CheckedTrb = Urb->Ring->RingSeg0; - - ASSERT (Urb->Ring->TrbNumber == CMD_RING_TRB_NUMBER || Urb->Ring->TrbNumber == TR_RING_TRB_NUMBER); + LIST_ENTRY *Entry; + LIST_ENTRY *Next; + URB *CheckedUrb; - for (Index = 0; Index < Urb->Ring->TrbNumber; Index++) { - if (Trb == CheckedTrb) { + EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) { + CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList); + if (IsTransferRingTrb (Xhc, Trb, CheckedUrb)) { + *Urb = CheckedUrb; return TRUE; } - CheckedTrb++; } return FALSE; } + /** Check the URB's execution result and update the URB's result accordingly. @@ -1131,7 +1132,7 @@ XhcCheckUrbResult ( // This way is used to avoid that those completed async transfer events don't get // handled in time and are flushed by newer coming events. // - if (IsTransferRingTrb (TRBPtr, Urb)) { + if (IsTransferRingTrb (Xhc, TRBPtr, Urb)) { CheckedUrb = Urb; } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) { CheckedUrb = AsyncUrb; -- 2.12.2.windows.2