* [staging/cadence-aarch64 PATCH v3 1/6] CadencePkg: Add libraries for Cadence CSP platform.
2017-06-22 9:31 [staging/cadence-aarch64 PATCH v3 0/6] CadencePkg: Add package for Cadence hardware IP support Scott Telford
@ 2017-06-22 9:31 ` Scott Telford
2017-06-22 14:50 ` Leif Lindholm
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 2/6] CadencePkg: Add library for Cadence UART Scott Telford
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Scott Telford @ 2017-06-22 9:31 UTC (permalink / raw)
To: edk2-devel, leif.lindholm, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
Add libraries (CadenceCspLib, CadenceCspSecLib,
CadenceCspResetSystemLib) to support the Cadence Configurable System
Platform (CSP) configured with a single ARM Cortex-A53, GIC-500,
Cadence UART and Cadence PCIe Root Complex.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford <stelford@cadence.com>
---
CadencePkg/Include/Library/CspSysReg.h | 37 ++++++
.../CadenceCspLib/AArch64/ArmPlatformHelper.S | 55 +++++++++
CadencePkg/Library/CadenceCspLib/CadenceCspLib.c | 133 +++++++++++++++++++++
CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf | 68 +++++++++++
.../Library/CadenceCspLib/CadenceCspLibMem.c | 116 ++++++++++++++++++
.../Library/CadenceCspLib/CadenceCspLibSec.inf | 52 ++++++++
.../CadenceCspResetSystemLib.c | 82 +++++++++++++
.../CadenceCspResetSystemLib.inf | 40 +++++++
.../Library/CadenceCspSecLib/AArch64/CspBoot.S | 49 ++++++++
.../Library/CadenceCspSecLib/AArch64/GicV3.S | 67 +++++++++++
.../Library/CadenceCspSecLib/CadenceCspSecLib.inf | 44 +++++++
CadencePkg/Library/CadenceCspSecLib/CspSec.c | 79 ++++++++++++
12 files changed, 822 insertions(+)
create mode 100644 CadencePkg/Include/Library/CspSysReg.h
create mode 100644 CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
create mode 100644 CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
create mode 100644 CadencePkg/Library/CadenceCspSecLib/CspSec.c
diff --git a/CadencePkg/Include/Library/CspSysReg.h b/CadencePkg/Include/Library/CspSysReg.h
new file mode 100644
index 0000000..4d3ac925
--- /dev/null
+++ b/CadencePkg/Include/Library/CspSysReg.h
@@ -0,0 +1,37 @@
+/** @file
+* Cadence CSP system register offsets.
+* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made
+* available under the terms and conditions of the BSD License which
+* accompanies this distribution. The full text of the license may be
+* found at http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CSP_SYS_REG_H__
+#define __CSP_SYS_REG_H__
+
+// Cadence CSP system register offsets
+#define CSP_SYSREG_VERSION 0x00
+#define CSP_SYSREG_CPU_FREQ 0x04
+#define CSP_SYSREG_STATUS 0x08
+#define CSP_SYSREG_RUN_STALL 0x0C
+#define CSP_SYSREG_SW_RESET 0x10
+#define CSP_SYSREG_CORE1_RESET 0x14
+#define CSP_SYSREG_SCRATCH_REG_0 0x18
+#define CSP_SYSREG_PROC_INTERRUPT 0x1C
+#define CSP_SYSREG_SCRATCH_REG_1 0x20
+#define CSP_SYSREG_SCRATCH_REG_2 0x24
+#define CSP_SYSREG_SCRATCH_REG_3 0x28
+#define CSP_SYSREG_SCRATCH_REG_4 0x2C
+#define CSP_SYSREG_SCRATCH_REG_5 0x30
+#define CSP_SYSREG_SCRATCH_REG_6 0x34
+#define CSP_SYSREG_SET_INTERRUPT 0x38
+#define CSP_SYSREG_CLR_INTERRUPT 0x3C
+#define CSP_SYSREG_DIP_SWITCHES 0x40
+
+#endif
diff --git a/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
new file mode 100644
index 0000000..8832673
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
@@ -0,0 +1,55 @@
+#
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+#include <AsmMacroIoLibV8.h>
+#include <Library/ArmLib.h>
+
+ASM_FUNC(ArmPlatformPeiBootAction)
+ ret
+
+//UINTN
+//ArmPlatformGetPrimaryCoreMpId (
+// VOID
+// );
+ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
+ MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
+ ret
+
+//UINTN
+//ArmPlatformIsPrimaryCore (
+// IN UINTN MpId
+// );
+ASM_FUNC(ArmPlatformIsPrimaryCore)
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
+ and x0, x0, x1
+ MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
+ cmp w0, w1
+ b.ne 1f
+ mov x0, #1
+ ret
+1:
+ mov x0, #0
+ ret
+
+//UINTN
+//ArmPlatformGetCorePosition (
+// IN UINTN MpId
+// );
+// With this function: CorePos = (ClusterId * 4) + CoreId
+ASM_FUNC(ArmPlatformGetCorePosition)
+ and x1, x0, #ARM_CORE_MASK
+ and x0, x0, #ARM_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
new file mode 100644
index 0000000..fc200a1
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
@@ -0,0 +1,133 @@
+/** @file
+*
+* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/CspSysReg.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+#include <Ppi/ArmMpCoreInfo.h>
+
+
+ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (EFI_PHYSICAL_ADDRESS)0,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
+
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
+
+/**
+ Initialize controllers that must setup in the normal world
+
+ This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
+ in the PEI phase.
+
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ UINTN CspScratchReg2;
+
+ if (!ArmPlatformIsPrimaryCore (MpId)) {
+ return RETURN_SUCCESS;
+ }
+
+ // CSP System Register initialisation
+ CspScratchReg2 = PcdGet64 (PcdCspSysRegBase) + CSP_SYSREG_SCRATCH_REG_2;
+ MmioWrite32 ((UINTN)CspScratchReg2, 0x1);
+ MmioWrite32 ((UINTN)CspScratchReg2, 0x3);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Initialize the system (or sometimes called permanent) memory
+
+ This memory is generally represented by the DRAM.
+
+**/
+VOID
+ArmPlatformInitializeSystemMemory (
+ VOID
+ )
+{
+}
+
+STATIC
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ if (ArmIsMpCore()) {
+ *CoreCount = sizeof(mArmPlatformNullMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+ *ArmCoreTable = mArmPlatformNullMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+}
+
+STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &gArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
+VOID
+ArmPlatformGetPlatformPpiList (
+ OUT UINTN *PpiListSize,
+ OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
+ )
+{
+ if (ArmIsMpCore()) {
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
+ } else {
+ *PpiListSize = 0;
+ *PpiList = NULL;
+ }
+}
+
diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
new file mode 100644
index 0000000..a09a89e
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
@@ -0,0 +1,68 @@
+#/* @file
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 1.25
+ BASE_NAME = CadenceCspLib
+ FILE_GUID = 13392a39-0fd2-4ec1-8541-1a7b5f0005d9
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ CadencePkg/CadenceCspPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ MemoryAllocationLib
+ SerialPortLib
+ DebugLib
+ HobLib
+
+[Sources.common]
+ CadenceCspLib.c
+ CadenceCspLibMem.c
+
+[Sources.AArch64]
+ AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ gArmTokenSpaceGuid.PcdSecureFdBaseAddress
+ gArmTokenSpaceGuid.PcdSecureFdSize
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegSize
+
+ gCadenceCspTokenSpaceGuid.PcdCspSerialBase
+ gCadenceCspTokenSpaceGuid.PcdCspSerialSize
+
+ gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress
+ gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
+ gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize
diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c b/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
new file mode 100644
index 0000000..5eccb7c
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
@@ -0,0 +1,116 @@
+/** @file
+*
+* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
+
+#define GICD_SZ SIZE_64KB
+#define GICR_SZ SIZE_128KB
+
+/**
+ Return the Virtual Memory Map of your platform
+
+ This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
+
+ @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
+ Virtual Memory mapping. This array must be ended by a zero-filled
+ entry
+
+**/
+VOID
+ArmPlatformGetVirtualMemoryMap (
+ IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
+ )
+{
+ UINTN Index = 0;
+ ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
+
+ ASSERT(VirtualMemoryMap != NULL);
+
+ VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
+ if (VirtualMemoryTable == NULL) {
+ return;
+ }
+ // SRAM
+ VirtualMemoryTable[Index].PhysicalBase = PcdGet64(PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdSystemMemoryBase);
+ VirtualMemoryTable[Index].Length = PcdGet64(PcdSystemMemorySize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CDNS UART
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdCspSerialBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdCspSerialBase);
+ VirtualMemoryTable[Index].Length = PcdGet32(PcdCspSerialSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // UEFI ROM (Secure)
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdSecureFdBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdSecureFdBaseAddress);
+ VirtualMemoryTable[Index].Length = PcdGet32(PcdSecureFdSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // UEFI ROM (Normal)
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdFdBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdFdBaseAddress);
+ VirtualMemoryTable[Index].Length = PcdGet32(PcdFdSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
+
+ // CSP SysRegs
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdCspSysRegBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdCspSysRegBase);
+ VirtualMemoryTable[Index].Length = PcdGet32(PcdCspSysRegSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // GIC Distributor
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdGicDistributorBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdGicDistributorBase);
+ VirtualMemoryTable[Index].Length = GICD_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // GIC Redistributor
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdGicRedistributorsBase);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdGicRedistributorsBase);
+ VirtualMemoryTable[Index].Length = GICR_SZ;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCIe RP
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdPcieRootPortBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdPcieRootPortBaseAddress);
+ VirtualMemoryTable[Index].Length = SIZE_8MB;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ //
+ // PCI Configuration Space (AXI region)
+ //
+ VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
+ VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciConfigurationSpaceSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // End of Table
+ VirtualMemoryTable[++Index].PhysicalBase = 0;
+ VirtualMemoryTable[Index].VirtualBase = 0;
+ VirtualMemoryTable[Index].Length = 0;
+ VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
+
+ ASSERT(Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
+
+ *VirtualMemoryMap = VirtualMemoryTable;
+}
diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf b/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
new file mode 100644
index 0000000..dd6c5c3
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
@@ -0,0 +1,52 @@
+#/* @file
+# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 1.25
+ BASE_NAME = CadenceCspLibSec
+ FILE_GUID = 3008d873-1400-48d8-abda-6ac9cce97246
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ CadencePkg/CadenceCspPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ ArmLib
+ DebugLib
+
+[Sources.common]
+ CadenceCspLib.c
+
+[Sources.AARCH64]
+ AArch64/ArmPlatformHelper.S
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegSize
+
+[Ppis]
+ gArmMpCoreInfoPpiGuid
diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
new file mode 100644
index 0000000..20ea1a6
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
@@ -0,0 +1,82 @@
+/** @file
+ Library to support ResetSystem Runtime call.
+
+ Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Library/BaseLib.h>
+#include <Library/CspSysReg.h>
+#include <Library/DebugLib.h>
+#include <Library/EfiResetSystemLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+/**
+ Resets the entire platform.
+
+ @param ResetType The type of reset to perform.
+ @param ResetStatus The status code for the reset.
+ @param DataSize The size, in bytes, of WatchdogData.
+ @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or
+ EfiResetShutdown the data buffer starts with a Null-terminated
+ Unicode string, optionally followed by additional binary data.
+
+**/
+EFI_STATUS
+EFIAPI
+LibResetSystem (
+ IN EFI_RESET_TYPE ResetType,
+ IN EFI_STATUS ResetStatus,
+ IN UINTN DataSize,
+ IN CHAR16 *ResetData OPTIONAL
+ )
+{
+ switch (ResetType) {
+ case EfiResetPlatformSpecific:
+ // Map the platform specific reset as reboot
+ case EfiResetWarm:
+ // Map a warm reset into a cold reset
+ case EfiResetShutdown:
+ // Map a shutdown into a cold reset
+ case EfiResetCold:
+ MmioWrite16((PcdGet64(PcdCspSysRegBase) + CSP_SYSREG_SW_RESET), 0xDEAD);
+ break;
+ default:
+ return EFI_INVALID_PARAMETER;
+ }
+
+ ASSERT(FALSE);
+ return EFI_UNSUPPORTED;
+}
+
+/**
+ Initialize any infrastructure required for LibResetSystem () to function.
+
+ @param ImageHandle The firmware allocated handle for the EFI image.
+ @param SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
+
+**/
+EFI_STATUS
+EFIAPI
+LibInitializeResetSystem (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ return EFI_SUCCESS;
+}
diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
new file mode 100644
index 0000000..66491ee
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
@@ -0,0 +1,40 @@
+#/** @file
+# Library to support ResetSystem Runtime call.
+#
+# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+#**/
+
+[Defines]
+ INF_VERSION = 1.25
+ BASE_NAME = CadenceCspResetSystemLib
+ FILE_GUID = 4b1bc734-7534-4baa-b33f-7f5caa743996
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = EfiResetSystemLib
+
+
+[Sources.common]
+ CadenceCspResetSystemLib.c
+
+[Packages]
+ CadencePkg/CadenceCspPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ IoLib
+ DebugLib
+ PcdLib
+
+[FixedPcd]
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S b/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
new file mode 100644
index 0000000..f0f411e
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
@@ -0,0 +1,49 @@
+//
+// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Base.h>
+#include <Library/ArmPlatformLib.h>
+#include <AutoGen.h>
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmPlatformSecBootAction)
+GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)
+
+/**
+ Call at the beginning of the platform boot up
+
+ This function allows the firmware platform to do extra actions at the early
+ stage of the platform power up.
+
+ Note: This function must be implemented in assembler as there is no stack set up yet
+
+**/
+ASM_PFX(ArmPlatformSecBootAction):
+ ret
+
+/**
+ Initialize the memory where the initial stacks will reside
+
+ This memory can contain the initial stacks (Secure and Secure Monitor stacks).
+ In some platform, this region is already initialized and the implementation of this function can
+ do nothing. This memory can also represent the Secure RAM.
+ This function is called before the satck has been set up. Its implementation must ensure the stack
+ pointer is not used (probably required to use assembly language)
+
+**/
+ASM_PFX(ArmPlatformSecBootMemoryInit):
+ // The SMC does not need to be initialized for RTSM
+ ret
diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S b/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
new file mode 100644
index 0000000..e136a8d
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
@@ -0,0 +1,67 @@
+//
+// Copyright (c) 2013-2014, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AsmMacroIoLibV8.h>
+#include <Chipset/AArch64.h>
+
+#ifndef __clang__
+// Register definitions used by GCC for GICv3 access.
+// These are defined by ARMCC, so keep them in the GCC specific code for now.
+#define ICC_SRE_EL2 S3_4_C12_C9_5
+#define ICC_SRE_EL3 S3_6_C12_C12_5
+#define ICC_CTLR_EL1 S3_0_C12_C12_4
+#define ICC_CTLR_EL3 S3_6_C12_C12_4
+#define ICC_PMR_EL1 S3_0_C4_C6_0
+#endif
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(InitializeGicV3)
+
+/* Initialize GICv3 */
+ASM_PFX(InitializeGicV3):
+ // In order to setup NS side we need to enable it first.
+ mrs x0, scr_el3
+ orr x0, x0, #1
+ msr scr_el3, x0
+
+ // Enable SRE at EL3 and ICC_SRE_EL2 access
+ mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE
+ mrs x1, ICC_SRE_EL3
+ orr x1, x1, x0
+ msr ICC_SRE_EL3, x1
+ isb
+
+ // Enable SRE at EL2 and ICC_SRE_EL1 access..
+ mrs x1, ICC_SRE_EL2
+ orr x1, x1, x0
+ msr ICC_SRE_EL2, x1
+ isb
+
+ // Configure CPU interface
+ msr ICC_CTLR_EL3, xzr
+ isb
+ msr ICC_CTLR_EL1, xzr
+ isb
+
+ // The MemoryMap view and Register view may not be consistent, So Set PMR again.
+ mov w1, #1 << 7 // allow NS access to GICC_PMR
+ msr ICC_PMR_EL1, x1
+ isb
+
+ // Remove the SCR.NS bit
+ mrs x0, scr_el3
+ and x0, x0, #~SCR_NS
+ msr scr_el3, x0
+ ret
diff --git a/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf b/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
new file mode 100644
index 0000000..1603ed1
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
@@ -0,0 +1,44 @@
+#/* @file
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 1.25
+ BASE_NAME = CadenceCspSecLib
+ FILE_GUID = 07a2577e-43fb-40d9-9833-415cb7feefab
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformSecLib
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ SerialPortLib
+
+[Sources.common]
+ CspSec.c
+
+[Sources.AARCH64]
+ AArch64/CspBoot.S
+ AArch64/GicV3.S
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
diff --git a/CadencePkg/Library/CadenceCspSecLib/CspSec.c b/CadencePkg/Library/CadenceCspSecLib/CspSec.c
new file mode 100644
index 0000000..7ef45c0
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspSecLib/CspSec.c
@@ -0,0 +1,79 @@
+/** @file
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/ArmGicLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+
+// Initialize GICv3
+VOID
+InitializeGicV3 (
+ VOID
+ );
+
+/**
+ Initialize the Secure peripherals and memory regions
+
+ If Trustzone is supported by your platform then this function makes the required initialization
+ of the secure peripherals and memory regions.
+
+**/
+VOID
+ArmPlatformSecTrustzoneInit (
+ IN UINTN MpId
+ )
+{
+ // No TZPC or TZASC on RTSM to initialize
+}
+
+/**
+ Initialize controllers that must setup at the early stage
+
+ Some peripherals must be initialized in Secure World.
+ For example, some L2x0 requires to be initialized in Secure World
+
+**/
+RETURN_STATUS
+ArmPlatformSecInitialize (
+ IN UINTN MpId
+ )
+{
+ // If it is not the primary core then there is nothing to do
+ if (!ArmPlatformIsPrimaryCore (MpId)) {
+ return RETURN_SUCCESS;
+ }
+
+ InitializeGicV3 ();
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Call before jumping to Normal World
+
+ This function allows the firmware platform to do extra actions before
+ jumping to the Normal World
+
+**/
+VOID
+ArmPlatformSecExtraAction (
+ IN UINTN MpId,
+ OUT UINTN* JumpAddress
+ )
+{
+ *JumpAddress = PcdGet64 (PcdFvBaseAddress);
+}
--
2.2.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [staging/cadence-aarch64 PATCH v3 1/6] CadencePkg: Add libraries for Cadence CSP platform.
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 1/6] CadencePkg: Add libraries for Cadence CSP platform Scott Telford
@ 2017-06-22 14:50 ` Leif Lindholm
2017-06-23 18:37 ` Ard Biesheuvel
0 siblings, 1 reply; 16+ messages in thread
From: Leif Lindholm @ 2017-06-22 14:50 UTC (permalink / raw)
To: Scott Telford
Cc: edk2-devel, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
On Thu, Jun 22, 2017 at 10:31:56AM +0100, Scott Telford wrote:
> Add libraries (CadenceCspLib, CadenceCspSecLib,
> CadenceCspResetSystemLib) to support the Cadence Configurable System
> Platform (CSP) configured with a single ARM Cortex-A53, GIC-500,
> Cadence UART and Cadence PCIe Root Complex.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford <stelford@cadence.com>
I'd like for Ard to comment on the bits he raised last time, but from
my point of view:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
/
Leif
> ---
> CadencePkg/Include/Library/CspSysReg.h | 37 ++++++
> .../CadenceCspLib/AArch64/ArmPlatformHelper.S | 55 +++++++++
> CadencePkg/Library/CadenceCspLib/CadenceCspLib.c | 133 +++++++++++++++++++++
> CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf | 68 +++++++++++
> .../Library/CadenceCspLib/CadenceCspLibMem.c | 116 ++++++++++++++++++
> .../Library/CadenceCspLib/CadenceCspLibSec.inf | 52 ++++++++
> .../CadenceCspResetSystemLib.c | 82 +++++++++++++
> .../CadenceCspResetSystemLib.inf | 40 +++++++
> .../Library/CadenceCspSecLib/AArch64/CspBoot.S | 49 ++++++++
> .../Library/CadenceCspSecLib/AArch64/GicV3.S | 67 +++++++++++
> .../Library/CadenceCspSecLib/CadenceCspSecLib.inf | 44 +++++++
> CadencePkg/Library/CadenceCspSecLib/CspSec.c | 79 ++++++++++++
> 12 files changed, 822 insertions(+)
> create mode 100644 CadencePkg/Include/Library/CspSysReg.h
> create mode 100644 CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
> create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
> create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
> create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
> create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
> create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
> create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
> create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
> create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
> create mode 100644 CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
> create mode 100644 CadencePkg/Library/CadenceCspSecLib/CspSec.c
>
> diff --git a/CadencePkg/Include/Library/CspSysReg.h b/CadencePkg/Include/Library/CspSysReg.h
> new file mode 100644
> index 0000000..4d3ac925
> --- /dev/null
> +++ b/CadencePkg/Include/Library/CspSysReg.h
> @@ -0,0 +1,37 @@
> +/** @file
> +* Cadence CSP system register offsets.
> +* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
> +*
> +* This program and the accompanying materials are licensed and made
> +* available under the terms and conditions of the BSD License which
> +* accompanies this distribution. The full text of the license may be
> +* found at http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __CSP_SYS_REG_H__
> +#define __CSP_SYS_REG_H__
> +
> +// Cadence CSP system register offsets
> +#define CSP_SYSREG_VERSION 0x00
> +#define CSP_SYSREG_CPU_FREQ 0x04
> +#define CSP_SYSREG_STATUS 0x08
> +#define CSP_SYSREG_RUN_STALL 0x0C
> +#define CSP_SYSREG_SW_RESET 0x10
> +#define CSP_SYSREG_CORE1_RESET 0x14
> +#define CSP_SYSREG_SCRATCH_REG_0 0x18
> +#define CSP_SYSREG_PROC_INTERRUPT 0x1C
> +#define CSP_SYSREG_SCRATCH_REG_1 0x20
> +#define CSP_SYSREG_SCRATCH_REG_2 0x24
> +#define CSP_SYSREG_SCRATCH_REG_3 0x28
> +#define CSP_SYSREG_SCRATCH_REG_4 0x2C
> +#define CSP_SYSREG_SCRATCH_REG_5 0x30
> +#define CSP_SYSREG_SCRATCH_REG_6 0x34
> +#define CSP_SYSREG_SET_INTERRUPT 0x38
> +#define CSP_SYSREG_CLR_INTERRUPT 0x3C
> +#define CSP_SYSREG_DIP_SWITCHES 0x40
> +
> +#endif
> diff --git a/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
> new file mode 100644
> index 0000000..8832673
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
> @@ -0,0 +1,55 @@
> +#
> +# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Library/ArmLib.h>
> +
> +ASM_FUNC(ArmPlatformPeiBootAction)
> + ret
> +
> +//UINTN
> +//ArmPlatformGetPrimaryCoreMpId (
> +// VOID
> +// );
> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
> + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
> + ret
> +
> +//UINTN
> +//ArmPlatformIsPrimaryCore (
> +// IN UINTN MpId
> +// );
> +ASM_FUNC(ArmPlatformIsPrimaryCore)
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
> + and x0, x0, x1
> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
> + cmp w0, w1
> + b.ne 1f
> + mov x0, #1
> + ret
> +1:
> + mov x0, #0
> + ret
> +
> +//UINTN
> +//ArmPlatformGetCorePosition (
> +// IN UINTN MpId
> +// );
> +// With this function: CorePos = (ClusterId * 4) + CoreId
> +ASM_FUNC(ArmPlatformGetCorePosition)
> + and x1, x0, #ARM_CORE_MASK
> + and x0, x0, #ARM_CLUSTER_MASK
> + add x0, x1, x0, LSR #6
> + ret
> +
> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
> new file mode 100644
> index 0000000..fc200a1
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
> @@ -0,0 +1,133 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmLib.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/CspSysReg.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +
> +#include <Ppi/ArmMpCoreInfo.h>
> +
> +
> +ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
> + {
> + // Cluster 0, Core 0
> + 0x0, 0x0,
> +
> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (EFI_PHYSICAL_ADDRESS)0,
> + (UINT64)0xFFFFFFFF
> + }
> +};
> +
> +
> +
> +/**
> + Return the current Boot Mode
> +
> + This function returns the boot reason on the platform
> +
> +**/
> +EFI_BOOT_MODE
> +ArmPlatformGetBootMode (
> + VOID
> + )
> +{
> + return BOOT_WITH_FULL_CONFIGURATION;
> +}
> +
> +/**
> + Initialize controllers that must setup in the normal world
> +
> + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
> + in the PEI phase.
> +
> +**/
> +RETURN_STATUS
> +ArmPlatformInitialize (
> + IN UINTN MpId
> + )
> +{
> + UINTN CspScratchReg2;
> +
> + if (!ArmPlatformIsPrimaryCore (MpId)) {
> + return RETURN_SUCCESS;
> + }
> +
> + // CSP System Register initialisation
> + CspScratchReg2 = PcdGet64 (PcdCspSysRegBase) + CSP_SYSREG_SCRATCH_REG_2;
> + MmioWrite32 ((UINTN)CspScratchReg2, 0x1);
> + MmioWrite32 ((UINTN)CspScratchReg2, 0x3);
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Initialize the system (or sometimes called permanent) memory
> +
> + This memory is generally represented by the DRAM.
> +
> +**/
> +VOID
> +ArmPlatformInitializeSystemMemory (
> + VOID
> + )
> +{
> +}
> +
> +STATIC
> +EFI_STATUS
> +PrePeiCoreGetMpCoreInfo (
> + OUT UINTN *CoreCount,
> + OUT ARM_CORE_INFO **ArmCoreTable
> + )
> +{
> + if (ArmIsMpCore()) {
> + *CoreCount = sizeof(mArmPlatformNullMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
> + *ArmCoreTable = mArmPlatformNullMpCoreInfoTable;
> + return EFI_SUCCESS;
> + } else {
> + return EFI_UNSUPPORTED;
> + }
> +}
> +
> +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
> +
> +STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
> + {
> + EFI_PEI_PPI_DESCRIPTOR_PPI,
> + &gArmMpCoreInfoPpiGuid,
> + &mMpCoreInfoPpi
> + }
> +};
> +
> +VOID
> +ArmPlatformGetPlatformPpiList (
> + OUT UINTN *PpiListSize,
> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
> + )
> +{
> + if (ArmIsMpCore()) {
> + *PpiListSize = sizeof(gPlatformPpiTable);
> + *PpiList = gPlatformPpiTable;
> + } else {
> + *PpiListSize = 0;
> + *PpiList = NULL;
> + }
> +}
> +
> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
> new file mode 100644
> index 0000000..a09a89e
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
> @@ -0,0 +1,68 @@
> +#/* @file
> +# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#*/
> +
> +[Defines]
> + INF_VERSION = 1.25
> + BASE_NAME = CadenceCspLib
> + FILE_GUID = 13392a39-0fd2-4ec1-8541-1a7b5f0005d9
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + CadencePkg/CadenceCspPkg.dec
> +
> +[LibraryClasses]
> + ArmLib
> + MemoryAllocationLib
> + SerialPortLib
> + DebugLib
> + HobLib
> +
> +[Sources.common]
> + CadenceCspLib.c
> + CadenceCspLibMem.c
> +
> +[Sources.AArch64]
> + AArch64/ArmPlatformHelper.S
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdSystemMemoryBase
> + gArmTokenSpaceGuid.PcdSystemMemorySize
> +
> + gArmTokenSpaceGuid.PcdSecureFdBaseAddress
> + gArmTokenSpaceGuid.PcdSecureFdSize
> + gArmTokenSpaceGuid.PcdFdBaseAddress
> + gArmTokenSpaceGuid.PcdFdSize
> +
> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> +
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> +
> + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
> + gCadenceCspTokenSpaceGuid.PcdCspSysRegSize
> +
> + gCadenceCspTokenSpaceGuid.PcdCspSerialBase
> + gCadenceCspTokenSpaceGuid.PcdCspSerialSize
> +
> + gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress
> + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
> + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize
> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c b/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
> new file mode 100644
> index 0000000..5eccb7c
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
> @@ -0,0 +1,116 @@
> +/** @file
> +*
> +* Copyright (c) 2011, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +
> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
> +
> +#define GICD_SZ SIZE_64KB
> +#define GICR_SZ SIZE_128KB
> +
> +/**
> + Return the Virtual Memory Map of your platform
> +
> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
> +
> + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
> + Virtual Memory mapping. This array must be ended by a zero-filled
> + entry
> +
> +**/
> +VOID
> +ArmPlatformGetVirtualMemoryMap (
> + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
> + )
> +{
> + UINTN Index = 0;
> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
> +
> + ASSERT(VirtualMemoryMap != NULL);
> +
> + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
> + if (VirtualMemoryTable == NULL) {
> + return;
> + }
> + // SRAM
> + VirtualMemoryTable[Index].PhysicalBase = PcdGet64(PcdSystemMemoryBase);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdSystemMemoryBase);
> + VirtualMemoryTable[Index].Length = PcdGet64(PcdSystemMemorySize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // CDNS UART
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdCspSerialBase);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdCspSerialBase);
> + VirtualMemoryTable[Index].Length = PcdGet32(PcdCspSerialSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // UEFI ROM (Secure)
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdSecureFdBaseAddress);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdSecureFdBaseAddress);
> + VirtualMemoryTable[Index].Length = PcdGet32(PcdSecureFdSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // UEFI ROM (Normal)
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdFdBaseAddress);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdFdBaseAddress);
> + VirtualMemoryTable[Index].Length = PcdGet32(PcdFdSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
> +
> + // CSP SysRegs
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdCspSysRegBase);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdCspSysRegBase);
> + VirtualMemoryTable[Index].Length = PcdGet32(PcdCspSysRegSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // GIC Distributor
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdGicDistributorBase);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdGicDistributorBase);
> + VirtualMemoryTable[Index].Length = GICD_SZ;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // GIC Redistributor
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdGicRedistributorsBase);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdGicRedistributorsBase);
> + VirtualMemoryTable[Index].Length = GICR_SZ;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // PCIe RP
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdPcieRootPortBaseAddress);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdPcieRootPortBaseAddress);
> + VirtualMemoryTable[Index].Length = SIZE_8MB;
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + //
> + // PCI Configuration Space (AXI region)
> + //
> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
> + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciConfigurationSpaceSize);
> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
> +
> + // End of Table
> + VirtualMemoryTable[++Index].PhysicalBase = 0;
> + VirtualMemoryTable[Index].VirtualBase = 0;
> + VirtualMemoryTable[Index].Length = 0;
> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
> +
> + ASSERT(Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
> +
> + *VirtualMemoryMap = VirtualMemoryTable;
> +}
> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf b/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
> new file mode 100644
> index 0000000..dd6c5c3
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
> @@ -0,0 +1,52 @@
> +#/* @file
> +# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#*/
> +
> +[Defines]
> + INF_VERSION = 1.25
> + BASE_NAME = CadenceCspLibSec
> + FILE_GUID = 3008d873-1400-48d8-abda-6ac9cce97246
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + CadencePkg/CadenceCspPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + ArmLib
> + DebugLib
> +
> +[Sources.common]
> + CadenceCspLib.c
> +
> +[Sources.AARCH64]
> + AArch64/ArmPlatformHelper.S
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdSystemMemoryBase
> + gArmTokenSpaceGuid.PcdSystemMemorySize
> + gArmTokenSpaceGuid.PcdFvBaseAddress
> +
> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
> + gArmTokenSpaceGuid.PcdArmPrimaryCore
> +
> + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
> + gCadenceCspTokenSpaceGuid.PcdCspSysRegSize
> +
> +[Ppis]
> + gArmMpCoreInfoPpiGuid
> diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
> new file mode 100644
> index 0000000..20ea1a6
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
> @@ -0,0 +1,82 @@
> +/** @file
> + Library to support ResetSystem Runtime call.
> +
> + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
> + Copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
> + Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <PiDxe.h>
> +
> +#include <Library/BaseLib.h>
> +#include <Library/CspSysReg.h>
> +#include <Library/DebugLib.h>
> +#include <Library/EfiResetSystemLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +
> +/**
> + Resets the entire platform.
> +
> + @param ResetType The type of reset to perform.
> + @param ResetStatus The status code for the reset.
> + @param DataSize The size, in bytes, of WatchdogData.
> + @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or
> + EfiResetShutdown the data buffer starts with a Null-terminated
> + Unicode string, optionally followed by additional binary data.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibResetSystem (
> + IN EFI_RESET_TYPE ResetType,
> + IN EFI_STATUS ResetStatus,
> + IN UINTN DataSize,
> + IN CHAR16 *ResetData OPTIONAL
> + )
> +{
> + switch (ResetType) {
> + case EfiResetPlatformSpecific:
> + // Map the platform specific reset as reboot
> + case EfiResetWarm:
> + // Map a warm reset into a cold reset
> + case EfiResetShutdown:
> + // Map a shutdown into a cold reset
> + case EfiResetCold:
> + MmioWrite16((PcdGet64(PcdCspSysRegBase) + CSP_SYSREG_SW_RESET), 0xDEAD);
> + break;
> + default:
> + return EFI_INVALID_PARAMETER;
> + }
> +
> + ASSERT(FALSE);
> + return EFI_UNSUPPORTED;
> +}
> +
> +/**
> + Initialize any infrastructure required for LibResetSystem () to function.
> +
> + @param ImageHandle The firmware allocated handle for the EFI image.
> + @param SystemTable A pointer to the EFI System Table.
> +
> + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
> +
> +**/
> +EFI_STATUS
> +EFIAPI
> +LibInitializeResetSystem (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + return EFI_SUCCESS;
> +}
> diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
> new file mode 100644
> index 0000000..66491ee
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
> @@ -0,0 +1,40 @@
> +#/** @file
> +# Library to support ResetSystem Runtime call.
> +#
> +# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 1.25
> + BASE_NAME = CadenceCspResetSystemLib
> + FILE_GUID = 4b1bc734-7534-4baa-b33f-7f5caa743996
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = EfiResetSystemLib
> +
> +
> +[Sources.common]
> + CadenceCspResetSystemLib.c
> +
> +[Packages]
> + CadencePkg/CadenceCspPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + IoLib
> + DebugLib
> + PcdLib
> +
> +[FixedPcd]
> + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
> diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S b/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
> new file mode 100644
> index 0000000..f0f411e
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
> @@ -0,0 +1,49 @@
> +//
> +// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
> +//
> +// This program and the accompanying materials
> +// are licensed and made available under the terms and conditions of the BSD License
> +// which accompanies this distribution. The full text of the license may be found at
> +// http://opensource.org/licenses/bsd-license.php
> +//
> +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +//
> +//
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Base.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <AutoGen.h>
> +
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(ArmPlatformSecBootAction)
> +GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)
> +
> +/**
> + Call at the beginning of the platform boot up
> +
> + This function allows the firmware platform to do extra actions at the early
> + stage of the platform power up.
> +
> + Note: This function must be implemented in assembler as there is no stack set up yet
> +
> +**/
> +ASM_PFX(ArmPlatformSecBootAction):
> + ret
> +
> +/**
> + Initialize the memory where the initial stacks will reside
> +
> + This memory can contain the initial stacks (Secure and Secure Monitor stacks).
> + In some platform, this region is already initialized and the implementation of this function can
> + do nothing. This memory can also represent the Secure RAM.
> + This function is called before the satck has been set up. Its implementation must ensure the stack
> + pointer is not used (probably required to use assembly language)
> +
> +**/
> +ASM_PFX(ArmPlatformSecBootMemoryInit):
> + // The SMC does not need to be initialized for RTSM
> + ret
> diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S b/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
> new file mode 100644
> index 0000000..e136a8d
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
> @@ -0,0 +1,67 @@
> +//
> +// Copyright (c) 2013-2014, ARM Limited. All rights reserved.
> +//
> +// This program and the accompanying materials
> +// are licensed and made available under the terms and conditions of the BSD License
> +// which accompanies this distribution. The full text of the license may be found at
> +// http://opensource.org/licenses/bsd-license.php
> +//
> +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +//
> +//
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Chipset/AArch64.h>
> +
> +#ifndef __clang__
> +// Register definitions used by GCC for GICv3 access.
> +// These are defined by ARMCC, so keep them in the GCC specific code for now.
> +#define ICC_SRE_EL2 S3_4_C12_C9_5
> +#define ICC_SRE_EL3 S3_6_C12_C12_5
> +#define ICC_CTLR_EL1 S3_0_C12_C12_4
> +#define ICC_CTLR_EL3 S3_6_C12_C12_4
> +#define ICC_PMR_EL1 S3_0_C4_C6_0
> +#endif
> +
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(InitializeGicV3)
> +
> +/* Initialize GICv3 */
> +ASM_PFX(InitializeGicV3):
> + // In order to setup NS side we need to enable it first.
> + mrs x0, scr_el3
> + orr x0, x0, #1
> + msr scr_el3, x0
> +
> + // Enable SRE at EL3 and ICC_SRE_EL2 access
> + mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE
> + mrs x1, ICC_SRE_EL3
> + orr x1, x1, x0
> + msr ICC_SRE_EL3, x1
> + isb
> +
> + // Enable SRE at EL2 and ICC_SRE_EL1 access..
> + mrs x1, ICC_SRE_EL2
> + orr x1, x1, x0
> + msr ICC_SRE_EL2, x1
> + isb
> +
> + // Configure CPU interface
> + msr ICC_CTLR_EL3, xzr
> + isb
> + msr ICC_CTLR_EL1, xzr
> + isb
> +
> + // The MemoryMap view and Register view may not be consistent, So Set PMR again.
> + mov w1, #1 << 7 // allow NS access to GICC_PMR
> + msr ICC_PMR_EL1, x1
> + isb
> +
> + // Remove the SCR.NS bit
> + mrs x0, scr_el3
> + and x0, x0, #~SCR_NS
> + msr scr_el3, x0
> + ret
> diff --git a/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf b/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
> new file mode 100644
> index 0000000..1603ed1
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
> @@ -0,0 +1,44 @@
> +#/* @file
> +# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#*/
> +
> +[Defines]
> + INF_VERSION = 1.25
> + BASE_NAME = CadenceCspSecLib
> + FILE_GUID = 07a2577e-43fb-40d9-9833-415cb7feefab
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = ArmPlatformSecLib
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + IoLib
> + ArmLib
> + SerialPortLib
> +
> +[Sources.common]
> + CspSec.c
> +
> +[Sources.AARCH64]
> + AArch64/CspBoot.S
> + AArch64/GicV3.S
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdFvBaseAddress
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
> diff --git a/CadencePkg/Library/CadenceCspSecLib/CspSec.c b/CadencePkg/Library/CadenceCspSecLib/CspSec.c
> new file mode 100644
> index 0000000..7ef45c0
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspSecLib/CspSec.c
> @@ -0,0 +1,79 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/ArmGicLib.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +
> +// Initialize GICv3
> +VOID
> +InitializeGicV3 (
> + VOID
> + );
> +
> +/**
> + Initialize the Secure peripherals and memory regions
> +
> + If Trustzone is supported by your platform then this function makes the required initialization
> + of the secure peripherals and memory regions.
> +
> +**/
> +VOID
> +ArmPlatformSecTrustzoneInit (
> + IN UINTN MpId
> + )
> +{
> + // No TZPC or TZASC on RTSM to initialize
> +}
> +
> +/**
> + Initialize controllers that must setup at the early stage
> +
> + Some peripherals must be initialized in Secure World.
> + For example, some L2x0 requires to be initialized in Secure World
> +
> +**/
> +RETURN_STATUS
> +ArmPlatformSecInitialize (
> + IN UINTN MpId
> + )
> +{
> + // If it is not the primary core then there is nothing to do
> + if (!ArmPlatformIsPrimaryCore (MpId)) {
> + return RETURN_SUCCESS;
> + }
> +
> + InitializeGicV3 ();
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> + Call before jumping to Normal World
> +
> + This function allows the firmware platform to do extra actions before
> + jumping to the Normal World
> +
> +**/
> +VOID
> +ArmPlatformSecExtraAction (
> + IN UINTN MpId,
> + OUT UINTN* JumpAddress
> + )
> +{
> + *JumpAddress = PcdGet64 (PcdFvBaseAddress);
> +}
> --
> 2.2.2
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [staging/cadence-aarch64 PATCH v3 1/6] CadencePkg: Add libraries for Cadence CSP platform.
2017-06-22 14:50 ` Leif Lindholm
@ 2017-06-23 18:37 ` Ard Biesheuvel
0 siblings, 0 replies; 16+ messages in thread
From: Ard Biesheuvel @ 2017-06-23 18:37 UTC (permalink / raw)
To: Leif Lindholm
Cc: Scott Telford, edk2-devel@lists.01.org, Graeme Gregory,
afish@apple.com, Kinney, Michael D
On 22 June 2017 at 14:50, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Thu, Jun 22, 2017 at 10:31:56AM +0100, Scott Telford wrote:
>> Add libraries (CadenceCspLib, CadenceCspSecLib,
>> CadenceCspResetSystemLib) to support the Cadence Configurable System
>> Platform (CSP) configured with a single ARM Cortex-A53, GIC-500,
>> Cadence UART and Cadence PCIe Root Complex.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Scott Telford <stelford@cadence.com>
>
> I'd like for Ard to comment on the bits he raised last time, but from
> my point of view:
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
Looks fine to me
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>> CadencePkg/Include/Library/CspSysReg.h | 37 ++++++
>> .../CadenceCspLib/AArch64/ArmPlatformHelper.S | 55 +++++++++
>> CadencePkg/Library/CadenceCspLib/CadenceCspLib.c | 133 +++++++++++++++++++++
>> CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf | 68 +++++++++++
>> .../Library/CadenceCspLib/CadenceCspLibMem.c | 116 ++++++++++++++++++
>> .../Library/CadenceCspLib/CadenceCspLibSec.inf | 52 ++++++++
>> .../CadenceCspResetSystemLib.c | 82 +++++++++++++
>> .../CadenceCspResetSystemLib.inf | 40 +++++++
>> .../Library/CadenceCspSecLib/AArch64/CspBoot.S | 49 ++++++++
>> .../Library/CadenceCspSecLib/AArch64/GicV3.S | 67 +++++++++++
>> .../Library/CadenceCspSecLib/CadenceCspSecLib.inf | 44 +++++++
>> CadencePkg/Library/CadenceCspSecLib/CspSec.c | 79 ++++++++++++
>> 12 files changed, 822 insertions(+)
>> create mode 100644 CadencePkg/Include/Library/CspSysReg.h
>> create mode 100644 CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
>> create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
>> create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
>> create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
>> create mode 100644 CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
>> create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
>> create mode 100644 CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
>> create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
>> create mode 100644 CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
>> create mode 100644 CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
>> create mode 100644 CadencePkg/Library/CadenceCspSecLib/CspSec.c
>>
>> diff --git a/CadencePkg/Include/Library/CspSysReg.h b/CadencePkg/Include/Library/CspSysReg.h
>> new file mode 100644
>> index 0000000..4d3ac925
>> --- /dev/null
>> +++ b/CadencePkg/Include/Library/CspSysReg.h
>> @@ -0,0 +1,37 @@
>> +/** @file
>> +* Cadence CSP system register offsets.
>> +* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
>> +*
>> +* This program and the accompanying materials are licensed and made
>> +* available under the terms and conditions of the BSD License which
>> +* accompanies this distribution. The full text of the license may be
>> +* found at http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#ifndef __CSP_SYS_REG_H__
>> +#define __CSP_SYS_REG_H__
>> +
>> +// Cadence CSP system register offsets
>> +#define CSP_SYSREG_VERSION 0x00
>> +#define CSP_SYSREG_CPU_FREQ 0x04
>> +#define CSP_SYSREG_STATUS 0x08
>> +#define CSP_SYSREG_RUN_STALL 0x0C
>> +#define CSP_SYSREG_SW_RESET 0x10
>> +#define CSP_SYSREG_CORE1_RESET 0x14
>> +#define CSP_SYSREG_SCRATCH_REG_0 0x18
>> +#define CSP_SYSREG_PROC_INTERRUPT 0x1C
>> +#define CSP_SYSREG_SCRATCH_REG_1 0x20
>> +#define CSP_SYSREG_SCRATCH_REG_2 0x24
>> +#define CSP_SYSREG_SCRATCH_REG_3 0x28
>> +#define CSP_SYSREG_SCRATCH_REG_4 0x2C
>> +#define CSP_SYSREG_SCRATCH_REG_5 0x30
>> +#define CSP_SYSREG_SCRATCH_REG_6 0x34
>> +#define CSP_SYSREG_SET_INTERRUPT 0x38
>> +#define CSP_SYSREG_CLR_INTERRUPT 0x3C
>> +#define CSP_SYSREG_DIP_SWITCHES 0x40
>> +
>> +#endif
>> diff --git a/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
>> new file mode 100644
>> index 0000000..8832673
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/AArch64/ArmPlatformHelper.S
>> @@ -0,0 +1,55 @@
>> +#
>> +# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#
>> +
>> +#include <AsmMacroIoLibV8.h>
>> +#include <Library/ArmLib.h>
>> +
>> +ASM_FUNC(ArmPlatformPeiBootAction)
>> + ret
>> +
>> +//UINTN
>> +//ArmPlatformGetPrimaryCoreMpId (
>> +// VOID
>> +// );
>> +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId)
>> + MOV32 (w0, FixedPcdGet32 (PcdArmPrimaryCore))
>> + ret
>> +
>> +//UINTN
>> +//ArmPlatformIsPrimaryCore (
>> +// IN UINTN MpId
>> +// );
>> +ASM_FUNC(ArmPlatformIsPrimaryCore)
>> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask))
>> + and x0, x0, x1
>> + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore))
>> + cmp w0, w1
>> + b.ne 1f
>> + mov x0, #1
>> + ret
>> +1:
>> + mov x0, #0
>> + ret
>> +
>> +//UINTN
>> +//ArmPlatformGetCorePosition (
>> +// IN UINTN MpId
>> +// );
>> +// With this function: CorePos = (ClusterId * 4) + CoreId
>> +ASM_FUNC(ArmPlatformGetCorePosition)
>> + and x1, x0, #ARM_CORE_MASK
>> + and x0, x0, #ARM_CLUSTER_MASK
>> + add x0, x1, x0, LSR #6
>> + ret
>> +
>> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
>> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
>> new file mode 100644
>> index 0000000..fc200a1
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.c
>> @@ -0,0 +1,133 @@
>> +/** @file
>> +*
>> +* Copyright (c) 2011-2012, ARM Limited. All rights reserved.
>> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#include <Library/ArmLib.h>
>> +#include <Library/ArmPlatformLib.h>
>> +#include <Library/CspSysReg.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +
>> +#include <Ppi/ArmMpCoreInfo.h>
>> +
>> +
>> +ARM_CORE_INFO mArmPlatformNullMpCoreInfoTable[] = {
>> + {
>> + // Cluster 0, Core 0
>> + 0x0, 0x0,
>> +
>> + // MP Core MailBox Set/Get/Clear Addresses and Clear Value
>> + (EFI_PHYSICAL_ADDRESS)0,
>> + (EFI_PHYSICAL_ADDRESS)0,
>> + (EFI_PHYSICAL_ADDRESS)0,
>> + (UINT64)0xFFFFFFFF
>> + }
>> +};
>> +
>> +
>> +
>> +/**
>> + Return the current Boot Mode
>> +
>> + This function returns the boot reason on the platform
>> +
>> +**/
>> +EFI_BOOT_MODE
>> +ArmPlatformGetBootMode (
>> + VOID
>> + )
>> +{
>> + return BOOT_WITH_FULL_CONFIGURATION;
>> +}
>> +
>> +/**
>> + Initialize controllers that must setup in the normal world
>> +
>> + This function is called by the ArmPlatformPkg/PrePi or ArmPlatformPkg/PlatformPei
>> + in the PEI phase.
>> +
>> +**/
>> +RETURN_STATUS
>> +ArmPlatformInitialize (
>> + IN UINTN MpId
>> + )
>> +{
>> + UINTN CspScratchReg2;
>> +
>> + if (!ArmPlatformIsPrimaryCore (MpId)) {
>> + return RETURN_SUCCESS;
>> + }
>> +
>> + // CSP System Register initialisation
>> + CspScratchReg2 = PcdGet64 (PcdCspSysRegBase) + CSP_SYSREG_SCRATCH_REG_2;
>> + MmioWrite32 ((UINTN)CspScratchReg2, 0x1);
>> + MmioWrite32 ((UINTN)CspScratchReg2, 0x3);
>> +
>> + return RETURN_SUCCESS;
>> +}
>> +
>> +/**
>> + Initialize the system (or sometimes called permanent) memory
>> +
>> + This memory is generally represented by the DRAM.
>> +
>> +**/
>> +VOID
>> +ArmPlatformInitializeSystemMemory (
>> + VOID
>> + )
>> +{
>> +}
>> +
>> +STATIC
>> +EFI_STATUS
>> +PrePeiCoreGetMpCoreInfo (
>> + OUT UINTN *CoreCount,
>> + OUT ARM_CORE_INFO **ArmCoreTable
>> + )
>> +{
>> + if (ArmIsMpCore()) {
>> + *CoreCount = sizeof(mArmPlatformNullMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
>> + *ArmCoreTable = mArmPlatformNullMpCoreInfoTable;
>> + return EFI_SUCCESS;
>> + } else {
>> + return EFI_UNSUPPORTED;
>> + }
>> +}
>> +
>> +STATIC ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
>> +
>> +STATIC EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
>> + {
>> + EFI_PEI_PPI_DESCRIPTOR_PPI,
>> + &gArmMpCoreInfoPpiGuid,
>> + &mMpCoreInfoPpi
>> + }
>> +};
>> +
>> +VOID
>> +ArmPlatformGetPlatformPpiList (
>> + OUT UINTN *PpiListSize,
>> + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
>> + )
>> +{
>> + if (ArmIsMpCore()) {
>> + *PpiListSize = sizeof(gPlatformPpiTable);
>> + *PpiList = gPlatformPpiTable;
>> + } else {
>> + *PpiListSize = 0;
>> + *PpiList = NULL;
>> + }
>> +}
>> +
>> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
>> new file mode 100644
>> index 0000000..a09a89e
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
>> @@ -0,0 +1,68 @@
>> +#/* @file
>> +# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
>> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#*/
>> +
>> +[Defines]
>> + INF_VERSION = 1.25
>> + BASE_NAME = CadenceCspLib
>> + FILE_GUID = 13392a39-0fd2-4ec1-8541-1a7b5f0005d9
>> + MODULE_TYPE = BASE
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = ArmPlatformLib
>> +
>> +[Packages]
>> + MdePkg/MdePkg.dec
>> + MdeModulePkg/MdeModulePkg.dec
>> + EmbeddedPkg/EmbeddedPkg.dec
>> + ArmPkg/ArmPkg.dec
>> + ArmPlatformPkg/ArmPlatformPkg.dec
>> + CadencePkg/CadenceCspPkg.dec
>> +
>> +[LibraryClasses]
>> + ArmLib
>> + MemoryAllocationLib
>> + SerialPortLib
>> + DebugLib
>> + HobLib
>> +
>> +[Sources.common]
>> + CadenceCspLib.c
>> + CadenceCspLibMem.c
>> +
>> +[Sources.AArch64]
>> + AArch64/ArmPlatformHelper.S
>> +
>> +[FixedPcd]
>> + gArmTokenSpaceGuid.PcdSystemMemoryBase
>> + gArmTokenSpaceGuid.PcdSystemMemorySize
>> +
>> + gArmTokenSpaceGuid.PcdSecureFdBaseAddress
>> + gArmTokenSpaceGuid.PcdSecureFdSize
>> + gArmTokenSpaceGuid.PcdFdBaseAddress
>> + gArmTokenSpaceGuid.PcdFdSize
>> +
>> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
>> + gArmTokenSpaceGuid.PcdArmPrimaryCore
>> +
>> + gArmTokenSpaceGuid.PcdGicDistributorBase
>> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
>> +
>> + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
>> + gCadenceCspTokenSpaceGuid.PcdCspSysRegSize
>> +
>> + gCadenceCspTokenSpaceGuid.PcdCspSerialBase
>> + gCadenceCspTokenSpaceGuid.PcdCspSerialSize
>> +
>> + gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress
>> + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
>> + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize
>> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c b/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
>> new file mode 100644
>> index 0000000..5eccb7c
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibMem.c
>> @@ -0,0 +1,116 @@
>> +/** @file
>> +*
>> +* Copyright (c) 2011, ARM Limited. All rights reserved.
>> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#include <Library/ArmPlatformLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/MemoryAllocationLib.h>
>> +#include <Library/PcdLib.h>
>> +
>> +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14
>> +
>> +#define GICD_SZ SIZE_64KB
>> +#define GICR_SZ SIZE_128KB
>> +
>> +/**
>> + Return the Virtual Memory Map of your platform
>> +
>> + This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform.
>> +
>> + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to-
>> + Virtual Memory mapping. This array must be ended by a zero-filled
>> + entry
>> +
>> +**/
>> +VOID
>> +ArmPlatformGetVirtualMemoryMap (
>> + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap
>> + )
>> +{
>> + UINTN Index = 0;
>> + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable;
>> +
>> + ASSERT(VirtualMemoryMap != NULL);
>> +
>> + VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS));
>> + if (VirtualMemoryTable == NULL) {
>> + return;
>> + }
>> + // SRAM
>> + VirtualMemoryTable[Index].PhysicalBase = PcdGet64(PcdSystemMemoryBase);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdSystemMemoryBase);
>> + VirtualMemoryTable[Index].Length = PcdGet64(PcdSystemMemorySize);
>> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>> +
>> + // CDNS UART
>> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdCspSerialBase);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdCspSerialBase);
>> + VirtualMemoryTable[Index].Length = PcdGet32(PcdCspSerialSize);
>> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> + // UEFI ROM (Secure)
>> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdSecureFdBaseAddress);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdSecureFdBaseAddress);
>> + VirtualMemoryTable[Index].Length = PcdGet32(PcdSecureFdSize);
>> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>> +
>> + // UEFI ROM (Normal)
>> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdFdBaseAddress);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdFdBaseAddress);
>> + VirtualMemoryTable[Index].Length = PcdGet32(PcdFdSize);
>> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK;
>> +
>> + // CSP SysRegs
>> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdCspSysRegBase);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdCspSysRegBase);
>> + VirtualMemoryTable[Index].Length = PcdGet32(PcdCspSysRegSize);
>> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> + // GIC Distributor
>> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdGicDistributorBase);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdGicDistributorBase);
>> + VirtualMemoryTable[Index].Length = GICD_SZ;
>> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> + // GIC Redistributor
>> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdGicRedistributorsBase);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdGicRedistributorsBase);
>> + VirtualMemoryTable[Index].Length = GICR_SZ;
>> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> + // PCIe RP
>> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64(PcdPcieRootPortBaseAddress);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64(PcdPcieRootPortBaseAddress);
>> + VirtualMemoryTable[Index].Length = SIZE_8MB;
>> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> + //
>> + // PCI Configuration Space (AXI region)
>> + //
>> + VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
>> + VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdPciConfigurationSpaceBaseAddress);
>> + VirtualMemoryTable[Index].Length = PcdGet64 (PcdPciConfigurationSpaceSize);
>> + VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
>> +
>> + // End of Table
>> + VirtualMemoryTable[++Index].PhysicalBase = 0;
>> + VirtualMemoryTable[Index].VirtualBase = 0;
>> + VirtualMemoryTable[Index].Length = 0;
>> + VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0;
>> +
>> + ASSERT(Index < MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS);
>> +
>> + *VirtualMemoryMap = VirtualMemoryTable;
>> +}
>> diff --git a/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf b/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
>> new file mode 100644
>> index 0000000..dd6c5c3
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
>> @@ -0,0 +1,52 @@
>> +#/* @file
>> +# Copyright (c) 2011-2012, ARM Limited. All rights reserved.
>> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#*/
>> +
>> +[Defines]
>> + INF_VERSION = 1.25
>> + BASE_NAME = CadenceCspLibSec
>> + FILE_GUID = 3008d873-1400-48d8-abda-6ac9cce97246
>> + MODULE_TYPE = BASE
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = ArmPlatformLib
>> +
>> +[Packages]
>> + ArmPkg/ArmPkg.dec
>> + ArmPlatformPkg/ArmPlatformPkg.dec
>> + CadencePkg/CadenceCspPkg.dec
>> + MdeModulePkg/MdeModulePkg.dec
>> + MdePkg/MdePkg.dec
>> +
>> +[LibraryClasses]
>> + ArmLib
>> + DebugLib
>> +
>> +[Sources.common]
>> + CadenceCspLib.c
>> +
>> +[Sources.AARCH64]
>> + AArch64/ArmPlatformHelper.S
>> +
>> +[FixedPcd]
>> + gArmTokenSpaceGuid.PcdSystemMemoryBase
>> + gArmTokenSpaceGuid.PcdSystemMemorySize
>> + gArmTokenSpaceGuid.PcdFvBaseAddress
>> +
>> + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
>> + gArmTokenSpaceGuid.PcdArmPrimaryCore
>> +
>> + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
>> + gCadenceCspTokenSpaceGuid.PcdCspSysRegSize
>> +
>> +[Ppis]
>> + gArmMpCoreInfoPpiGuid
>> diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
>> new file mode 100644
>> index 0000000..20ea1a6
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.c
>> @@ -0,0 +1,82 @@
>> +/** @file
>> + Library to support ResetSystem Runtime call.
>> +
>> + Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
>> + Copyright (c) 2013, ARM Ltd. All rights reserved.<BR>
>> + Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +
>> + This program and the accompanying materials
>> + are licensed and made available under the terms and conditions of the BSD License
>> + which accompanies this distribution. The full text of the license may be found at
>> + http://opensource.org/licenses/bsd-license.php
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <PiDxe.h>
>> +
>> +#include <Library/BaseLib.h>
>> +#include <Library/CspSysReg.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/EfiResetSystemLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +
>> +/**
>> + Resets the entire platform.
>> +
>> + @param ResetType The type of reset to perform.
>> + @param ResetStatus The status code for the reset.
>> + @param DataSize The size, in bytes, of WatchdogData.
>> + @param ResetData For a ResetType of EfiResetCold, EfiResetWarm, or
>> + EfiResetShutdown the data buffer starts with a Null-terminated
>> + Unicode string, optionally followed by additional binary data.
>> +
>> +**/
>> +EFI_STATUS
>> +EFIAPI
>> +LibResetSystem (
>> + IN EFI_RESET_TYPE ResetType,
>> + IN EFI_STATUS ResetStatus,
>> + IN UINTN DataSize,
>> + IN CHAR16 *ResetData OPTIONAL
>> + )
>> +{
>> + switch (ResetType) {
>> + case EfiResetPlatformSpecific:
>> + // Map the platform specific reset as reboot
>> + case EfiResetWarm:
>> + // Map a warm reset into a cold reset
>> + case EfiResetShutdown:
>> + // Map a shutdown into a cold reset
>> + case EfiResetCold:
>> + MmioWrite16((PcdGet64(PcdCspSysRegBase) + CSP_SYSREG_SW_RESET), 0xDEAD);
>> + break;
>> + default:
>> + return EFI_INVALID_PARAMETER;
>> + }
>> +
>> + ASSERT(FALSE);
>> + return EFI_UNSUPPORTED;
>> +}
>> +
>> +/**
>> + Initialize any infrastructure required for LibResetSystem () to function.
>> +
>> + @param ImageHandle The firmware allocated handle for the EFI image.
>> + @param SystemTable A pointer to the EFI System Table.
>> +
>> + @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.
>> +
>> +**/
>> +EFI_STATUS
>> +EFIAPI
>> +LibInitializeResetSystem (
>> + IN EFI_HANDLE ImageHandle,
>> + IN EFI_SYSTEM_TABLE *SystemTable
>> + )
>> +{
>> + return EFI_SUCCESS;
>> +}
>> diff --git a/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
>> new file mode 100644
>> index 0000000..66491ee
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
>> @@ -0,0 +1,40 @@
>> +#/** @file
>> +# Library to support ResetSystem Runtime call.
>> +#
>> +# Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#
>> +#**/
>> +
>> +[Defines]
>> + INF_VERSION = 1.25
>> + BASE_NAME = CadenceCspResetSystemLib
>> + FILE_GUID = 4b1bc734-7534-4baa-b33f-7f5caa743996
>> + MODULE_TYPE = BASE
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = EfiResetSystemLib
>> +
>> +
>> +[Sources.common]
>> + CadenceCspResetSystemLib.c
>> +
>> +[Packages]
>> + CadencePkg/CadenceCspPkg.dec
>> + EmbeddedPkg/EmbeddedPkg.dec
>> + MdePkg/MdePkg.dec
>> +
>> +[LibraryClasses]
>> + IoLib
>> + DebugLib
>> + PcdLib
>> +
>> +[FixedPcd]
>> + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
>> diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S b/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
>> new file mode 100644
>> index 0000000..f0f411e
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/CspBoot.S
>> @@ -0,0 +1,49 @@
>> +//
>> +// Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
>> +//
>> +// This program and the accompanying materials
>> +// are licensed and made available under the terms and conditions of the BSD License
>> +// which accompanies this distribution. The full text of the license may be found at
>> +// http://opensource.org/licenses/bsd-license.php
>> +//
>> +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +//
>> +//
>> +
>> +#include <AsmMacroIoLibV8.h>
>> +#include <Base.h>
>> +#include <Library/ArmPlatformLib.h>
>> +#include <AutoGen.h>
>> +
>> +.text
>> +.align 3
>> +
>> +GCC_ASM_EXPORT(ArmPlatformSecBootAction)
>> +GCC_ASM_EXPORT(ArmPlatformSecBootMemoryInit)
>> +
>> +/**
>> + Call at the beginning of the platform boot up
>> +
>> + This function allows the firmware platform to do extra actions at the early
>> + stage of the platform power up.
>> +
>> + Note: This function must be implemented in assembler as there is no stack set up yet
>> +
>> +**/
>> +ASM_PFX(ArmPlatformSecBootAction):
>> + ret
>> +
>> +/**
>> + Initialize the memory where the initial stacks will reside
>> +
>> + This memory can contain the initial stacks (Secure and Secure Monitor stacks).
>> + In some platform, this region is already initialized and the implementation of this function can
>> + do nothing. This memory can also represent the Secure RAM.
>> + This function is called before the satck has been set up. Its implementation must ensure the stack
>> + pointer is not used (probably required to use assembly language)
>> +
>> +**/
>> +ASM_PFX(ArmPlatformSecBootMemoryInit):
>> + // The SMC does not need to be initialized for RTSM
>> + ret
>> diff --git a/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S b/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
>> new file mode 100644
>> index 0000000..e136a8d
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSecLib/AArch64/GicV3.S
>> @@ -0,0 +1,67 @@
>> +//
>> +// Copyright (c) 2013-2014, ARM Limited. All rights reserved.
>> +//
>> +// This program and the accompanying materials
>> +// are licensed and made available under the terms and conditions of the BSD License
>> +// which accompanies this distribution. The full text of the license may be found at
>> +// http://opensource.org/licenses/bsd-license.php
>> +//
>> +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +//
>> +//
>> +
>> +#include <AsmMacroIoLibV8.h>
>> +#include <Chipset/AArch64.h>
>> +
>> +#ifndef __clang__
>> +// Register definitions used by GCC for GICv3 access.
>> +// These are defined by ARMCC, so keep them in the GCC specific code for now.
>> +#define ICC_SRE_EL2 S3_4_C12_C9_5
>> +#define ICC_SRE_EL3 S3_6_C12_C12_5
>> +#define ICC_CTLR_EL1 S3_0_C12_C12_4
>> +#define ICC_CTLR_EL3 S3_6_C12_C12_4
>> +#define ICC_PMR_EL1 S3_0_C4_C6_0
>> +#endif
>> +
>> +.text
>> +.align 3
>> +
>> +GCC_ASM_EXPORT(InitializeGicV3)
>> +
>> +/* Initialize GICv3 */
>> +ASM_PFX(InitializeGicV3):
>> + // In order to setup NS side we need to enable it first.
>> + mrs x0, scr_el3
>> + orr x0, x0, #1
>> + msr scr_el3, x0
>> +
>> + // Enable SRE at EL3 and ICC_SRE_EL2 access
>> + mov x0, #((1 << 3) | (1 << 0)) // Enable | SRE
>> + mrs x1, ICC_SRE_EL3
>> + orr x1, x1, x0
>> + msr ICC_SRE_EL3, x1
>> + isb
>> +
>> + // Enable SRE at EL2 and ICC_SRE_EL1 access..
>> + mrs x1, ICC_SRE_EL2
>> + orr x1, x1, x0
>> + msr ICC_SRE_EL2, x1
>> + isb
>> +
>> + // Configure CPU interface
>> + msr ICC_CTLR_EL3, xzr
>> + isb
>> + msr ICC_CTLR_EL1, xzr
>> + isb
>> +
>> + // The MemoryMap view and Register view may not be consistent, So Set PMR again.
>> + mov w1, #1 << 7 // allow NS access to GICC_PMR
>> + msr ICC_PMR_EL1, x1
>> + isb
>> +
>> + // Remove the SCR.NS bit
>> + mrs x0, scr_el3
>> + and x0, x0, #~SCR_NS
>> + msr scr_el3, x0
>> + ret
>> diff --git a/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf b/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
>> new file mode 100644
>> index 0000000..1603ed1
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
>> @@ -0,0 +1,44 @@
>> +#/* @file
>> +# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
>> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#*/
>> +
>> +[Defines]
>> + INF_VERSION = 1.25
>> + BASE_NAME = CadenceCspSecLib
>> + FILE_GUID = 07a2577e-43fb-40d9-9833-415cb7feefab
>> + MODULE_TYPE = BASE
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = ArmPlatformSecLib
>> +
>> +[Packages]
>> + ArmPkg/ArmPkg.dec
>> + ArmPlatformPkg/ArmPlatformPkg.dec
>> + EmbeddedPkg/EmbeddedPkg.dec
>> + MdeModulePkg/MdeModulePkg.dec
>> + MdePkg/MdePkg.dec
>> +
>> +[LibraryClasses]
>> + IoLib
>> + ArmLib
>> + SerialPortLib
>> +
>> +[Sources.common]
>> + CspSec.c
>> +
>> +[Sources.AARCH64]
>> + AArch64/CspBoot.S
>> + AArch64/GicV3.S
>> +
>> +[FixedPcd]
>> + gArmTokenSpaceGuid.PcdFvBaseAddress
>> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
>> diff --git a/CadencePkg/Library/CadenceCspSecLib/CspSec.c b/CadencePkg/Library/CadenceCspSecLib/CspSec.c
>> new file mode 100644
>> index 0000000..7ef45c0
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSecLib/CspSec.c
>> @@ -0,0 +1,79 @@
>> +/** @file
>> +*
>> +* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
>> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#include <Library/ArmGicLib.h>
>> +#include <Library/ArmPlatformLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +
>> +// Initialize GICv3
>> +VOID
>> +InitializeGicV3 (
>> + VOID
>> + );
>> +
>> +/**
>> + Initialize the Secure peripherals and memory regions
>> +
>> + If Trustzone is supported by your platform then this function makes the required initialization
>> + of the secure peripherals and memory regions.
>> +
>> +**/
>> +VOID
>> +ArmPlatformSecTrustzoneInit (
>> + IN UINTN MpId
>> + )
>> +{
>> + // No TZPC or TZASC on RTSM to initialize
>> +}
>> +
>> +/**
>> + Initialize controllers that must setup at the early stage
>> +
>> + Some peripherals must be initialized in Secure World.
>> + For example, some L2x0 requires to be initialized in Secure World
>> +
>> +**/
>> +RETURN_STATUS
>> +ArmPlatformSecInitialize (
>> + IN UINTN MpId
>> + )
>> +{
>> + // If it is not the primary core then there is nothing to do
>> + if (!ArmPlatformIsPrimaryCore (MpId)) {
>> + return RETURN_SUCCESS;
>> + }
>> +
>> + InitializeGicV3 ();
>> +
>> + return RETURN_SUCCESS;
>> +}
>> +
>> +/**
>> + Call before jumping to Normal World
>> +
>> + This function allows the firmware platform to do extra actions before
>> + jumping to the Normal World
>> +
>> +**/
>> +VOID
>> +ArmPlatformSecExtraAction (
>> + IN UINTN MpId,
>> + OUT UINTN* JumpAddress
>> + )
>> +{
>> + *JumpAddress = PcdGet64 (PcdFvBaseAddress);
>> +}
>> --
>> 2.2.2
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [staging/cadence-aarch64 PATCH v3 2/6] CadencePkg: Add library for Cadence UART.
2017-06-22 9:31 [staging/cadence-aarch64 PATCH v3 0/6] CadencePkg: Add package for Cadence hardware IP support Scott Telford
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 1/6] CadencePkg: Add libraries for Cadence CSP platform Scott Telford
@ 2017-06-22 9:31 ` Scott Telford
2017-06-22 15:02 ` Leif Lindholm
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex Scott Telford
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Scott Telford @ 2017-06-22 9:31 UTC (permalink / raw)
To: edk2-devel, leif.lindholm, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
Add serial port library to support the Cadence IP6528 UART used in the
Cadence CSP platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford <stelford@cadence.com>
---
CadencePkg/Include/Library/CspSerialPortLib.h | 86 ++++
.../CadenceCspSerialPortLib/CspSerialPortLib.c | 523 +++++++++++++++++++++
.../CadenceCspSerialPortLib/CspSerialPortLib.inf | 52 ++
.../CadenceCspSerialPortLib/CspSerialPortLib.uni | Bin 0 -> 1622 bytes
4 files changed, 661 insertions(+)
create mode 100644 CadencePkg/Include/Library/CspSerialPortLib.h
create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni
diff --git a/CadencePkg/Include/Library/CspSerialPortLib.h b/CadencePkg/Include/Library/CspSerialPortLib.h
new file mode 100644
index 0000000..46fa0d8
--- /dev/null
+++ b/CadencePkg/Include/Library/CspSerialPortLib.h
@@ -0,0 +1,86 @@
+/** @file
+* Serial Port Library for Cadence IP6528 UART.
+* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
+*
+* This program and the accompanying materials are licensed and made
+* available under the terms and conditions of the BSD License which
+* accompanies this distribution. The full text of the license may be
+* found at http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CSP_SERIAL_PORT_LIB_H__
+#define __CSP_SERIAL_PORT_LIB_H__
+
+// Cadence UART register offsets
+#define CSP_UART_CR 0x00 // Control
+#define CSP_UART_MR 0x04 // Mode
+#define CSP_UART_IER 0x08 // Interrupt enable
+#define CSP_UART_IDR 0x0C // Interrupt disable
+#define CSP_UART_IMR 0x10 // Interrupt mask
+#define CSP_UART_CISR 0x14 // Channel interrupt status
+#define CSP_UART_BRGR 0x18 // Baud rate generator
+#define CSP_UART_RTOR 0x1C // Rx Timeout
+#define CSP_UART_RTRIG 0x20 // Rx FIFO trigger level
+#define CSP_UART_MCR 0x24 // Modem control
+#define CSP_UART_MSR 0x28 // Modem status
+#define CSP_UART_CSR 0x2C // Channel status
+#define CSP_UART_FIFO 0x30 // FIFO (Tx/Rx)
+#define CSP_UART_BDIV 0x34 // Baud rate divider
+#define CSP_UART_FDEL 0x38 // Flow delay
+#define CSP_UART_PMIN 0x3C // IR min received pulse width
+#define CSP_UART_PWID 0x40 // IR transmitted pulse Width
+#define CSP_UART_TTRIG 0x44 // Tx FIFO trigger level
+
+
+// Control Register Bit Definitions
+#define CSP_UART_CR_STPBRK 0x00000100 // Stop Tx break
+#define CSP_UART_CR_STTBRK 0x00000080 // Start Tx break
+#define CSP_UART_CR_RSTTO 0x00000040 // Restart Rx timeout Counter
+#define CSP_UART_CR_TXDIS 0x00000020 // Tx disable
+#define CSP_UART_CR_TXEN 0x00000010 // Tx enable
+#define CSP_UART_CR_RXDIS 0x00000008 // Rx disable
+#define CSP_UART_CR_RXEN 0x00000004 // Rx enable
+#define CSP_UART_CR_TXRES 0x00000002 // Tx reset
+#define CSP_UART_CR_RXRES 0x00000001 // Rx reset
+
+
+// Mode register bit definitions
+#define CSP_UART_MR_CLKS 0x00000001 // Baud rate /8 pre-scalar
+#define CSP_UART_MR_CHMODE_LLB 0x00000200 // Local loopback mode
+#define CSP_UART_MR_CHMODE_NML 0x00000000 // Normal mode
+
+#define CSP_UART_MR_CHRL_6 0x00000006 // 6 databits
+#define CSP_UART_MR_CHRL_7 0x00000004 // 7 databits
+#define CSP_UART_MR_CHRL_8 0x00000000 // 8 databits
+
+#define CSP_UART_MR_PAR_NONE 0x00000020 // No parity mode
+#define CSP_UART_MR_PAR_MARK 0x00000018 // Mark parity mode
+#define CSP_UART_MR_PAR_SPACE 0x00000010 // Space parity mode
+#define CSP_UART_MR_PAR_ODD 0x00000008 // Odd parity mode
+#define CSP_UART_MR_PAR_EVEN 0x00000000 // Even parity mode
+
+#define CSP_UART_MR_NBSTOP_1 0x00000000 // 1 stop bit
+#define CSP_UART_MR_NBSTOP_2 0x00000080 // 2 stop bits
+
+// Modem control register bit definitions
+#define CSP_UART_MCR_DTR 0x00000001 // DTR control
+#define CSP_UART_MCR_RTS 0x00000002 // RTS control
+#define CSP_UART_MCR_FCM 0x00000020 // Auto flow control
+
+// Modem status register bit definitions
+#define CSP_UART_MSR_FCMS 0x00000100 // Auto flow control status
+#define CSP_UART_MSR_DCD 0x00000080 // DCD status
+#define CSP_UART_MSR_RI 0x00000040 // RI status
+#define CSP_UART_MSR_DSR 0x00000020 // DSR status
+#define CSP_UART_MSR_CTS 0x00000010 // CTS status
+
+// Channel status register bit definitions
+#define CSP_UART_CSR_REMPTY 0x00000002 // Rx FIFO empty
+#define CSP_UART_CSR_TEMPTY 0x00000008 // Tx FIFO empty
+#define CSP_UART_CSR_TFUL 0x00000010 // Tx FIFO full
+
+#endif
diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
new file mode 100644
index 0000000..9a9e14a
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
@@ -0,0 +1,523 @@
+/** @file
+ Serial Port Library for Cadence IP6528 UART.
+ Copyright (c) 2015-2017, Cadence Design Systems, Inc. All rights reserved.
+
+ Based on:
+
+ Null Serial Port library instance with empty functions.
+
+ Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Base.h>
+#include <Library/BaseLib.h>
+#include <Library/CspSerialPortLib.h>
+#include <Library/CspSysReg.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+
+
+RETURN_STATUS
+EFIAPI
+CspUartInitializePort (
+ IN UINTN UartBase,
+ IN OUT UINT64 *BaudRate,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+);
+VOID CspUartPutChar (IN UINTN UartBase, IN UINT8 Char);
+UINT8 CspUartGetChar (IN UINTN UartBase);
+
+/**
+ Initialize the serial device hardware.
+
+ If no initialization is required, then return RETURN_SUCCESS.
+ If the serial device was successfully initialized, then return RETURN_SUCCESS.
+ If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
+
+ @retval RETURN_SUCCESS The serial device was initialized.
+ @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortInitialize (
+ VOID
+ )
+{
+ UINT64 BaudRate;
+ EFI_PARITY_TYPE Parity;
+ UINT8 DataBits;
+ EFI_STOP_BITS_TYPE StopBits;
+
+ BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
+ Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
+ DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
+ StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
+
+ return CspUartInitializePort (
+ (UINTN)FixedPcdGet64 (PcdCspSerialBase),
+ &BaudRate,
+ &Parity,
+ &DataBits,
+ &StopBits
+ );
+}
+
+/**
+ Set new attributes to UART.
+
+ @param BaudRate The baud rate of the serial device. If the
+ baud rate is not supported, the speed will
+ be reduced down to the nearest supported one
+ and the variable's value will be updated
+ accordingly.
+ @param ReceiveFifoDepth The number of characters the device will
+ buffer on input. If the specified value is
+ not supported, the variable's value will
+ be reduced down to the nearest supported one.
+ @param Timeout If applicable, the number of microseconds the
+ device will wait before timing out a Read or
+ a Write operation.
+ @param Parity If applicable, this is the EFI_PARITY_TYPE
+ that is computed or checked as each character
+ is transmitted or received. If the device
+ does not support parity, the value is the
+ default parity value.
+ @param DataBits The number of data bits in each character
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
+ of stop bits per character. If the device
+ does not support stop bits, the value is the
+ default stop bit value.
+
+ @retval EFI_SUCCESS All attributes were set correctly.
+ @retval EFI_INVALID_PARAMETERS One or more attributes has an unsupported
+ value.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetAttributes (
+ IN OUT UINT64 *BaudRate,
+ IN OUT UINT32 *ReceiveFifoDepth,
+ IN OUT UINT32 *Timeout,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ return CspUartInitializePort (
+ (UINTN)FixedPcdGet64 (PcdCspSerialBase),
+ BaudRate,
+ Parity,
+ DataBits,
+ StopBits
+ );
+}
+
+/**
+ Write data from buffer to serial device.
+
+ Writes NumberOfBytes data bytes from Buffer to the serial device.
+ The number of bytes actually written to the serial device is returned.
+ If the return value is less than NumberOfBytes, then the write operation failed.
+ If Buffer is NULL, then ASSERT().
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer The pointer to the data buffer to be written.
+ @param NumberOfBytes The number of bytes to written to the serial device.
+
+ @retval 0 NumberOfBytes is 0.
+ @retval >0 The number of bytes written to the serial device.
+ If this value is less than NumberOfBytes, then the read operation failed.
+
+**/
+UINTN
+EFIAPI
+SerialPortWrite (
+ IN UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN i;
+ for (i = 0; i < NumberOfBytes; i++) {
+ CspUartPutChar ((UINTN)PcdGet64 (PcdCspSerialBase), Buffer[i]);
+ }
+ return i;
+}
+
+
+/**
+ Read data from serial device and save the datas in buffer.
+
+ Reads NumberOfBytes data bytes from a serial device into the buffer
+ specified by Buffer. The number of bytes actually read is returned.
+ If the return value is less than NumberOfBytes, then the rest operation failed.
+ If Buffer is NULL, then ASSERT().
+ If NumberOfBytes is zero, then return 0.
+
+ @param Buffer The pointer to the data buffer to store the data read from the serial device.
+ @param NumberOfBytes The number of bytes which will be read.
+
+ @retval 0 Read data failed; No data is to be read.
+ @retval >0 The actual number of bytes read from serial device.
+
+**/
+UINTN
+EFIAPI
+SerialPortRead (
+ OUT UINT8 *Buffer,
+ IN UINTN NumberOfBytes
+)
+{
+ UINTN i;
+ for (i = 0; i < NumberOfBytes; i++) {
+ Buffer[i] = CspUartGetChar ((UINTN)PcdGet64 (PcdCspSerialBase));
+ }
+ return i;
+}
+
+/**
+ Polls a serial device to see if there is any data waiting to be read.
+
+ Polls a serial device to see if there is any data waiting to be read.
+ If there is data waiting to be read from the serial device, then TRUE is returned.
+ If there is no data waiting to be read from the serial device, then FALSE is returned.
+
+ @retval TRUE Data is waiting to be read from the serial device.
+ @retval FALSE There is no data waiting to be read from the serial device.
+
+**/
+BOOLEAN
+EFIAPI
+SerialPortPoll (
+ VOID
+ )
+{
+ return (MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase + CSP_UART_CSR))) &
+ CSP_UART_CSR_REMPTY) ? FALSE : TRUE;
+}
+
+/**
+
+ Assert or deassert the control signals on a serial port.
+ The following control signals are set according their bit settings :
+ . Request to Send
+ . Data Terminal Ready
+
+ @param[in] Control The following bits are taken into account :
+ . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
+ "Request To Send" control signal if this bit is
+ equal to one/zero.
+ . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
+ the "Data Terminal Ready" control signal if this
+ bit is equal to one/zero.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
+ the hardware loopback if this bit is equal to
+ one/zero.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
+ disable the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals.
+
+ @retval RETURN_SUCCESS The new control bits were set on the device.
+ @retval RETURN_UNSUPPORTED The device does not support this operation.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortSetControl (
+ IN UINT32 Control
+ )
+{
+ UINT32 Bits;
+
+ if (Control & (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE |
+ EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE )) {
+ return RETURN_UNSUPPORTED;
+ }
+
+ Bits = MmioRead32 (PcdGet64 (PcdCspSerialBase) + CSP_UART_MCR);
+
+ if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
+ Bits |= CSP_UART_MCR_RTS;
+ } else {
+ Bits &= ~CSP_UART_MCR_RTS;
+ }
+
+ if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {
+ Bits |= CSP_UART_MCR_DTR;
+ } else {
+ Bits &= ~CSP_UART_MCR_DTR;
+ }
+
+ if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
+ Bits |= CSP_UART_MCR_FCM;
+ } else {
+ Bits &= CSP_UART_MCR_FCM;
+ }
+
+ MmioWrite32 ((PcdGet64 (PcdCspSerialBase) + CSP_UART_MCR), Bits);
+
+ return RETURN_SUCCESS;
+}
+
+/**
+
+ Retrieve the status of the control bits on a serial device.
+
+ @param[out] Control Status of the control bits on a serial device :
+
+ . EFI_SERIAL_DATA_CLEAR_TO_SEND,
+ EFI_SERIAL_DATA_SET_READY,
+ EFI_SERIAL_RING_INDICATE,
+ EFI_SERIAL_CARRIER_DETECT,
+ EFI_SERIAL_REQUEST_TO_SEND,
+ EFI_SERIAL_DATA_TERMINAL_READY
+ are all related to the DTE (Data Terminal Equipment)
+ and DCE (Data Communication Equipment) modes of
+ operation of the serial device.
+ . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
+ receive buffer is empty, 0 otherwise.
+ . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
+ transmit buffer is empty, 0 otherwise.
+ . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
+ the hardware loopback is enabled (the output feeds
+ the receive buffer), 0 otherwise.
+ . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one
+ if a loopback is accomplished by software, else 0.
+ . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
+ one if the hardware flow control based on CTS (Clear
+ To Send) and RTS (Ready To Send) control signals is
+ enabled, 0 otherwise.
+
+ @retval RETURN_SUCCESS The control bits were read from the device.
+
+**/
+RETURN_STATUS
+EFIAPI
+SerialPortGetControl (
+ OUT UINT32 *Control
+ )
+{
+ UINT32 ModemStatusReg;
+ UINT32 ModemCtrlReg;
+ UINT32 ChanStatusReg;
+
+ ModemCtrlReg = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase) +
+ CSP_UART_MCR));
+ ModemStatusReg = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase) +
+ CSP_UART_MSR));
+ ChanStatusReg = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase) +
+ CSP_UART_CSR));
+
+ *Control = 0;
+
+ if ((ModemStatusReg & CSP_UART_MSR_CTS) == CSP_UART_MSR_CTS) {
+ *Control |= EFI_SERIAL_CLEAR_TO_SEND;
+ }
+
+ if ((ModemStatusReg & CSP_UART_MSR_DSR) == CSP_UART_MSR_DSR) {
+ *Control |= EFI_SERIAL_DATA_SET_READY;
+ }
+
+ if ((ModemStatusReg & CSP_UART_MSR_RI) == CSP_UART_MSR_RI) {
+ *Control |= EFI_SERIAL_RING_INDICATE;
+ }
+
+ if ((ModemStatusReg & CSP_UART_MSR_DCD) == CSP_UART_MSR_DCD) {
+ *Control |= EFI_SERIAL_CARRIER_DETECT;
+ }
+
+ if ((ModemCtrlReg & CSP_UART_MCR_RTS) == CSP_UART_MCR_RTS) {
+ *Control |= EFI_SERIAL_REQUEST_TO_SEND;
+ }
+
+ if ((ModemCtrlReg & CSP_UART_MCR_DTR) == CSP_UART_MCR_DTR) {
+ *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
+ }
+
+ if ((ChanStatusReg & CSP_UART_CSR_REMPTY) == CSP_UART_CSR_REMPTY) {
+ *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
+ }
+
+ if ((ChanStatusReg & CSP_UART_CSR_TEMPTY) == CSP_UART_CSR_TEMPTY) {
+ *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
+ }
+
+ if ((ModemCtrlReg & CSP_UART_MCR_FCM) == CSP_UART_MCR_FCM) {
+ *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
+ }
+
+ return RETURN_SUCCESS;
+}
+
+
+/**
+
+ Initialise the serial port to the specified settings.
+ The serial port is re-configured only if the specified settings
+ are different from the current settings.
+ All unspecified settings will be set to the default values.
+
+ @param UartBase The base address of the serial device.
+ @param BaudRate The baud rate of the serial device. If the
+ baud rate is not supported, the speed will be
+ reduced to the nearest supported one and the
+ variable's value will be updated accordingly.
+ @param Parity If applicable, this is the EFI_PARITY_TYPE
+ that is computed or checked as each character
+ is transmitted or received. If the device
+ does not support parity, the value is the
+ default parity value.
+ @param DataBits The number of data bits in each character.
+ @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
+ of stop bits per character.
+ If the device does not support stop bits, the
+ value is the default stop bit value.
+
+ @retval RETURN_SUCCESS All attributes were set correctly on the
+ serial device.
+ @retval RETURN_INVALID_PARAMETER One or more of the attributes has an
+ unsupported value.
+
+**/
+RETURN_STATUS
+EFIAPI
+CspUartInitializePort (
+ IN UINTN UartBase,
+ IN OUT UINT64 *BaudRate,
+ IN OUT EFI_PARITY_TYPE *Parity,
+ IN OUT UINT8 *DataBits,
+ IN OUT EFI_STOP_BITS_TYPE *StopBits
+ )
+{
+ UINT32 RegVal = 0;
+ UINT32 BaudDivisor = 0;
+
+ // Wait for Tx FIFO to empty before initializing
+ if (!(MmioRead32 (UartBase + CSP_UART_CR) & CSP_UART_CR_TXDIS)) {
+ while (!(MmioRead32 (UartBase + CSP_UART_CSR) & CSP_UART_CSR_TEMPTY))
+ ;
+ }
+
+ // Disable Tx/Rx before setting baud rate
+ RegVal = MmioRead32 (UartBase + CSP_UART_CR);
+ RegVal |= CSP_UART_CR_TXDIS | CSP_UART_CR_RXDIS;
+ MmioWrite32 ((UartBase + CSP_UART_CR), RegVal);
+
+ // Set baud rate
+ UINT32 SelClk = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSysRegBase) +
+ CSP_SYSREG_CPU_FREQ));
+ UINT32 BDiv = 0;
+
+ if (SelClk < 0x1800000) {
+ BaudDivisor = 1;
+ } else {
+ BaudDivisor = 8;
+ }
+ MmioWrite32 ((UartBase + CSP_UART_BRGR), BaudDivisor);
+ BDiv = (SelClk + ((*BaudRate * BaudDivisor) / 2)) / (*BaudRate * BaudDivisor);
+ MmioWrite32 ((UartBase + CSP_UART_BDIV), (BDiv - 1));
+
+ // Reset and enable Tx/Rx
+ RegVal = MmioRead32 (UartBase + CSP_UART_CR);
+ RegVal &= ~(CSP_UART_CR_TXDIS | CSP_UART_CR_RXDIS);
+ RegVal |= CSP_UART_CR_TXEN | CSP_UART_CR_TXRES | \
+ CSP_UART_CR_RXEN | CSP_UART_CR_RXRES;;
+ MmioWrite32 ((UartBase + CSP_UART_CR), RegVal);
+
+ RegVal = MmioRead32 (UartBase + CSP_UART_MR) & 1;
+
+ //
+ // Data Bits
+ //
+ switch (*DataBits) {
+ case 0:
+ *DataBits = 8;
+ case 8:
+ RegVal |= CSP_UART_MR_CHRL_8;
+ break;
+ case 7:
+ RegVal |= CSP_UART_MR_CHRL_7;
+ break;
+ case 6:
+ RegVal |= CSP_UART_MR_CHRL_6;
+ break;
+ default:
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Stop Bits
+ //
+ switch (*StopBits) {
+ case DefaultStopBits:
+ *StopBits = OneStopBit;
+ case OneStopBit:
+ RegVal |= CSP_UART_MR_NBSTOP_1;
+ break;
+ case TwoStopBits:
+ RegVal |= CSP_UART_MR_NBSTOP_2;
+ break;
+ default:
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ //
+ // Parity
+ //
+ switch (*Parity) {
+ case DefaultParity:
+ *Parity = NoParity;
+ case NoParity:
+ RegVal |= CSP_UART_MR_PAR_NONE;
+ break;
+ case EvenParity:
+ RegVal |= CSP_UART_MR_PAR_EVEN;
+ break;
+ case OddParity:
+ RegVal |= CSP_UART_MR_PAR_ODD;
+ break;
+ case MarkParity:
+ RegVal |= CSP_UART_MR_PAR_MARK;
+ break;
+ case SpaceParity:
+ RegVal |= CSP_UART_MR_PAR_SPACE;
+ break;
+ default:
+ return RETURN_INVALID_PARAMETER;
+ }
+
+ MmioWrite32 ((UartBase + CSP_UART_MR), RegVal);
+
+ return RETURN_SUCCESS;
+}
+
+VOID CspUartPutChar (IN UINTN UartBase, IN UINT8 Char)
+{
+ while ((MmioRead32 (UartBase + CSP_UART_CSR) & CSP_UART_CSR_TFUL)
+ == CSP_UART_CSR_TFUL)
+ ;
+ MmioWrite8 (UartBase + CSP_UART_FIFO, Char);
+}
+
+UINT8 CspUartGetChar (IN UINTN UartBase)
+{
+ while ((MmioRead32 (UartBase + CSP_UART_CSR) & CSP_UART_CSR_REMPTY)
+ == CSP_UART_CSR_REMPTY)
+ ;
+ return MmioRead8 (UartBase + CSP_UART_FIFO);
+}
+
diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
new file mode 100644
index 0000000..46ea8f9
--- /dev/null
+++ b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
@@ -0,0 +1,52 @@
+## @file
+# Serial Port Library for Cadence IP6528 UART.
+#
+# Based on:
+#
+# Null instance of Serial Port Library with empty functions.
+#
+# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (C) 2017 Cadence Design Systems. All rights reserved worldwide.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 1.25
+ BASE_NAME = CspSerialPortLib
+ MODULE_UNI_FILE = CspSerialPortLib.uni
+ FILE_GUID = C456789-8897-411a-91F8-7D7E45837146
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = SerialPortLib
+
+[Sources]
+ CspSerialPortLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ CadencePkg/CadenceCspPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ DebugLib
+ IoLib
+ BaseLib
+ PcdLib
+
+[FixedPcd]
+ gCadenceCspTokenSpaceGuid.PcdCspSerialBase
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
+
diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni
new file mode 100644
index 0000000000000000000000000000000000000000..60434d42366ee99f53da028381deff21250cfda8
GIT binary patch
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literal 0
HcmV?d00001
--
2.2.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [staging/cadence-aarch64 PATCH v3 2/6] CadencePkg: Add library for Cadence UART.
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 2/6] CadencePkg: Add library for Cadence UART Scott Telford
@ 2017-06-22 15:02 ` Leif Lindholm
2017-06-23 18:38 ` Ard Biesheuvel
0 siblings, 1 reply; 16+ messages in thread
From: Leif Lindholm @ 2017-06-22 15:02 UTC (permalink / raw)
To: Scott Telford
Cc: edk2-devel, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
On Thu, Jun 22, 2017 at 10:31:57AM +0100, Scott Telford wrote:
> Add serial port library to support the Cadence IP6528 UART used in the
> Cadence CSP platform.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford <stelford@cadence.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> CadencePkg/Include/Library/CspSerialPortLib.h | 86 ++++
> .../CadenceCspSerialPortLib/CspSerialPortLib.c | 523 +++++++++++++++++++++
> .../CadenceCspSerialPortLib/CspSerialPortLib.inf | 52 ++
> .../CadenceCspSerialPortLib/CspSerialPortLib.uni | Bin 0 -> 1622 bytes
> 4 files changed, 661 insertions(+)
> create mode 100644 CadencePkg/Include/Library/CspSerialPortLib.h
> create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
> create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
> create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni
>
> diff --git a/CadencePkg/Include/Library/CspSerialPortLib.h b/CadencePkg/Include/Library/CspSerialPortLib.h
> new file mode 100644
> index 0000000..46fa0d8
> --- /dev/null
> +++ b/CadencePkg/Include/Library/CspSerialPortLib.h
> @@ -0,0 +1,86 @@
> +/** @file
> +* Serial Port Library for Cadence IP6528 UART.
> +* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
> +*
> +* This program and the accompanying materials are licensed and made
> +* available under the terms and conditions of the BSD License which
> +* accompanies this distribution. The full text of the license may be
> +* found at http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __CSP_SERIAL_PORT_LIB_H__
> +#define __CSP_SERIAL_PORT_LIB_H__
> +
> +// Cadence UART register offsets
> +#define CSP_UART_CR 0x00 // Control
> +#define CSP_UART_MR 0x04 // Mode
> +#define CSP_UART_IER 0x08 // Interrupt enable
> +#define CSP_UART_IDR 0x0C // Interrupt disable
> +#define CSP_UART_IMR 0x10 // Interrupt mask
> +#define CSP_UART_CISR 0x14 // Channel interrupt status
> +#define CSP_UART_BRGR 0x18 // Baud rate generator
> +#define CSP_UART_RTOR 0x1C // Rx Timeout
> +#define CSP_UART_RTRIG 0x20 // Rx FIFO trigger level
> +#define CSP_UART_MCR 0x24 // Modem control
> +#define CSP_UART_MSR 0x28 // Modem status
> +#define CSP_UART_CSR 0x2C // Channel status
> +#define CSP_UART_FIFO 0x30 // FIFO (Tx/Rx)
> +#define CSP_UART_BDIV 0x34 // Baud rate divider
> +#define CSP_UART_FDEL 0x38 // Flow delay
> +#define CSP_UART_PMIN 0x3C // IR min received pulse width
> +#define CSP_UART_PWID 0x40 // IR transmitted pulse Width
> +#define CSP_UART_TTRIG 0x44 // Tx FIFO trigger level
> +
> +
> +// Control Register Bit Definitions
> +#define CSP_UART_CR_STPBRK 0x00000100 // Stop Tx break
> +#define CSP_UART_CR_STTBRK 0x00000080 // Start Tx break
> +#define CSP_UART_CR_RSTTO 0x00000040 // Restart Rx timeout Counter
> +#define CSP_UART_CR_TXDIS 0x00000020 // Tx disable
> +#define CSP_UART_CR_TXEN 0x00000010 // Tx enable
> +#define CSP_UART_CR_RXDIS 0x00000008 // Rx disable
> +#define CSP_UART_CR_RXEN 0x00000004 // Rx enable
> +#define CSP_UART_CR_TXRES 0x00000002 // Tx reset
> +#define CSP_UART_CR_RXRES 0x00000001 // Rx reset
> +
> +
> +// Mode register bit definitions
> +#define CSP_UART_MR_CLKS 0x00000001 // Baud rate /8 pre-scalar
> +#define CSP_UART_MR_CHMODE_LLB 0x00000200 // Local loopback mode
> +#define CSP_UART_MR_CHMODE_NML 0x00000000 // Normal mode
> +
> +#define CSP_UART_MR_CHRL_6 0x00000006 // 6 databits
> +#define CSP_UART_MR_CHRL_7 0x00000004 // 7 databits
> +#define CSP_UART_MR_CHRL_8 0x00000000 // 8 databits
> +
> +#define CSP_UART_MR_PAR_NONE 0x00000020 // No parity mode
> +#define CSP_UART_MR_PAR_MARK 0x00000018 // Mark parity mode
> +#define CSP_UART_MR_PAR_SPACE 0x00000010 // Space parity mode
> +#define CSP_UART_MR_PAR_ODD 0x00000008 // Odd parity mode
> +#define CSP_UART_MR_PAR_EVEN 0x00000000 // Even parity mode
> +
> +#define CSP_UART_MR_NBSTOP_1 0x00000000 // 1 stop bit
> +#define CSP_UART_MR_NBSTOP_2 0x00000080 // 2 stop bits
> +
> +// Modem control register bit definitions
> +#define CSP_UART_MCR_DTR 0x00000001 // DTR control
> +#define CSP_UART_MCR_RTS 0x00000002 // RTS control
> +#define CSP_UART_MCR_FCM 0x00000020 // Auto flow control
> +
> +// Modem status register bit definitions
> +#define CSP_UART_MSR_FCMS 0x00000100 // Auto flow control status
> +#define CSP_UART_MSR_DCD 0x00000080 // DCD status
> +#define CSP_UART_MSR_RI 0x00000040 // RI status
> +#define CSP_UART_MSR_DSR 0x00000020 // DSR status
> +#define CSP_UART_MSR_CTS 0x00000010 // CTS status
> +
> +// Channel status register bit definitions
> +#define CSP_UART_CSR_REMPTY 0x00000002 // Rx FIFO empty
> +#define CSP_UART_CSR_TEMPTY 0x00000008 // Tx FIFO empty
> +#define CSP_UART_CSR_TFUL 0x00000010 // Tx FIFO full
> +
> +#endif
> diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
> new file mode 100644
> index 0000000..9a9e14a
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
> @@ -0,0 +1,523 @@
> +/** @file
> + Serial Port Library for Cadence IP6528 UART.
> + Copyright (c) 2015-2017, Cadence Design Systems, Inc. All rights reserved.
> +
> + Based on:
> +
> + Null Serial Port library instance with empty functions.
> +
> + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
> + This program and the accompanying materials
> + are licensed and made available under the terms and conditions of the BSD License
> + which accompanies this distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +
> +#include <Base.h>
> +#include <Library/BaseLib.h>
> +#include <Library/CspSerialPortLib.h>
> +#include <Library/CspSysReg.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/SerialPortLib.h>
> +
> +
> +RETURN_STATUS
> +EFIAPI
> +CspUartInitializePort (
> + IN UINTN UartBase,
> + IN OUT UINT64 *BaudRate,
> + IN OUT EFI_PARITY_TYPE *Parity,
> + IN OUT UINT8 *DataBits,
> + IN OUT EFI_STOP_BITS_TYPE *StopBits
> +);
> +VOID CspUartPutChar (IN UINTN UartBase, IN UINT8 Char);
> +UINT8 CspUartGetChar (IN UINTN UartBase);
> +
> +/**
> + Initialize the serial device hardware.
> +
> + If no initialization is required, then return RETURN_SUCCESS.
> + If the serial device was successfully initialized, then return RETURN_SUCCESS.
> + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
> +
> + @retval RETURN_SUCCESS The serial device was initialized.
> + @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortInitialize (
> + VOID
> + )
> +{
> + UINT64 BaudRate;
> + EFI_PARITY_TYPE Parity;
> + UINT8 DataBits;
> + EFI_STOP_BITS_TYPE StopBits;
> +
> + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
> + Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
> + DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
> + StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
> +
> + return CspUartInitializePort (
> + (UINTN)FixedPcdGet64 (PcdCspSerialBase),
> + &BaudRate,
> + &Parity,
> + &DataBits,
> + &StopBits
> + );
> +}
> +
> +/**
> + Set new attributes to UART.
> +
> + @param BaudRate The baud rate of the serial device. If the
> + baud rate is not supported, the speed will
> + be reduced down to the nearest supported one
> + and the variable's value will be updated
> + accordingly.
> + @param ReceiveFifoDepth The number of characters the device will
> + buffer on input. If the specified value is
> + not supported, the variable's value will
> + be reduced down to the nearest supported one.
> + @param Timeout If applicable, the number of microseconds the
> + device will wait before timing out a Read or
> + a Write operation.
> + @param Parity If applicable, this is the EFI_PARITY_TYPE
> + that is computed or checked as each character
> + is transmitted or received. If the device
> + does not support parity, the value is the
> + default parity value.
> + @param DataBits The number of data bits in each character
> + @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
> + of stop bits per character. If the device
> + does not support stop bits, the value is the
> + default stop bit value.
> +
> + @retval EFI_SUCCESS All attributes were set correctly.
> + @retval EFI_INVALID_PARAMETERS One or more attributes has an unsupported
> + value.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortSetAttributes (
> + IN OUT UINT64 *BaudRate,
> + IN OUT UINT32 *ReceiveFifoDepth,
> + IN OUT UINT32 *Timeout,
> + IN OUT EFI_PARITY_TYPE *Parity,
> + IN OUT UINT8 *DataBits,
> + IN OUT EFI_STOP_BITS_TYPE *StopBits
> + )
> +{
> + return CspUartInitializePort (
> + (UINTN)FixedPcdGet64 (PcdCspSerialBase),
> + BaudRate,
> + Parity,
> + DataBits,
> + StopBits
> + );
> +}
> +
> +/**
> + Write data from buffer to serial device.
> +
> + Writes NumberOfBytes data bytes from Buffer to the serial device.
> + The number of bytes actually written to the serial device is returned.
> + If the return value is less than NumberOfBytes, then the write operation failed.
> + If Buffer is NULL, then ASSERT().
> + If NumberOfBytes is zero, then return 0.
> +
> + @param Buffer The pointer to the data buffer to be written.
> + @param NumberOfBytes The number of bytes to written to the serial device.
> +
> + @retval 0 NumberOfBytes is 0.
> + @retval >0 The number of bytes written to the serial device.
> + If this value is less than NumberOfBytes, then the read operation failed.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortWrite (
> + IN UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> +)
> +{
> + UINTN i;
> + for (i = 0; i < NumberOfBytes; i++) {
> + CspUartPutChar ((UINTN)PcdGet64 (PcdCspSerialBase), Buffer[i]);
> + }
> + return i;
> +}
> +
> +
> +/**
> + Read data from serial device and save the datas in buffer.
> +
> + Reads NumberOfBytes data bytes from a serial device into the buffer
> + specified by Buffer. The number of bytes actually read is returned.
> + If the return value is less than NumberOfBytes, then the rest operation failed.
> + If Buffer is NULL, then ASSERT().
> + If NumberOfBytes is zero, then return 0.
> +
> + @param Buffer The pointer to the data buffer to store the data read from the serial device.
> + @param NumberOfBytes The number of bytes which will be read.
> +
> + @retval 0 Read data failed; No data is to be read.
> + @retval >0 The actual number of bytes read from serial device.
> +
> +**/
> +UINTN
> +EFIAPI
> +SerialPortRead (
> + OUT UINT8 *Buffer,
> + IN UINTN NumberOfBytes
> +)
> +{
> + UINTN i;
> + for (i = 0; i < NumberOfBytes; i++) {
> + Buffer[i] = CspUartGetChar ((UINTN)PcdGet64 (PcdCspSerialBase));
> + }
> + return i;
> +}
> +
> +/**
> + Polls a serial device to see if there is any data waiting to be read.
> +
> + Polls a serial device to see if there is any data waiting to be read.
> + If there is data waiting to be read from the serial device, then TRUE is returned.
> + If there is no data waiting to be read from the serial device, then FALSE is returned.
> +
> + @retval TRUE Data is waiting to be read from the serial device.
> + @retval FALSE There is no data waiting to be read from the serial device.
> +
> +**/
> +BOOLEAN
> +EFIAPI
> +SerialPortPoll (
> + VOID
> + )
> +{
> + return (MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase + CSP_UART_CSR))) &
> + CSP_UART_CSR_REMPTY) ? FALSE : TRUE;
> +}
> +
> +/**
> +
> + Assert or deassert the control signals on a serial port.
> + The following control signals are set according their bit settings :
> + . Request to Send
> + . Data Terminal Ready
> +
> + @param[in] Control The following bits are taken into account :
> + . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
> + "Request To Send" control signal if this bit is
> + equal to one/zero.
> + . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
> + the "Data Terminal Ready" control signal if this
> + bit is equal to one/zero.
> + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
> + the hardware loopback if this bit is equal to
> + one/zero.
> + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
> + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
> + disable the hardware flow control based on CTS (Clear
> + To Send) and RTS (Ready To Send) control signals.
> +
> + @retval RETURN_SUCCESS The new control bits were set on the device.
> + @retval RETURN_UNSUPPORTED The device does not support this operation.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortSetControl (
> + IN UINT32 Control
> + )
> +{
> + UINT32 Bits;
> +
> + if (Control & (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE |
> + EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE )) {
> + return RETURN_UNSUPPORTED;
> + }
> +
> + Bits = MmioRead32 (PcdGet64 (PcdCspSerialBase) + CSP_UART_MCR);
> +
> + if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
> + Bits |= CSP_UART_MCR_RTS;
> + } else {
> + Bits &= ~CSP_UART_MCR_RTS;
> + }
> +
> + if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {
> + Bits |= CSP_UART_MCR_DTR;
> + } else {
> + Bits &= ~CSP_UART_MCR_DTR;
> + }
> +
> + if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
> + Bits |= CSP_UART_MCR_FCM;
> + } else {
> + Bits &= CSP_UART_MCR_FCM;
> + }
> +
> + MmioWrite32 ((PcdGet64 (PcdCspSerialBase) + CSP_UART_MCR), Bits);
> +
> + return RETURN_SUCCESS;
> +}
> +
> +/**
> +
> + Retrieve the status of the control bits on a serial device.
> +
> + @param[out] Control Status of the control bits on a serial device :
> +
> + . EFI_SERIAL_DATA_CLEAR_TO_SEND,
> + EFI_SERIAL_DATA_SET_READY,
> + EFI_SERIAL_RING_INDICATE,
> + EFI_SERIAL_CARRIER_DETECT,
> + EFI_SERIAL_REQUEST_TO_SEND,
> + EFI_SERIAL_DATA_TERMINAL_READY
> + are all related to the DTE (Data Terminal Equipment)
> + and DCE (Data Communication Equipment) modes of
> + operation of the serial device.
> + . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
> + receive buffer is empty, 0 otherwise.
> + . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
> + transmit buffer is empty, 0 otherwise.
> + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
> + the hardware loopback is enabled (the output feeds
> + the receive buffer), 0 otherwise.
> + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one
> + if a loopback is accomplished by software, else 0.
> + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
> + one if the hardware flow control based on CTS (Clear
> + To Send) and RTS (Ready To Send) control signals is
> + enabled, 0 otherwise.
> +
> + @retval RETURN_SUCCESS The control bits were read from the device.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +SerialPortGetControl (
> + OUT UINT32 *Control
> + )
> +{
> + UINT32 ModemStatusReg;
> + UINT32 ModemCtrlReg;
> + UINT32 ChanStatusReg;
> +
> + ModemCtrlReg = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase) +
> + CSP_UART_MCR));
> + ModemStatusReg = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase) +
> + CSP_UART_MSR));
> + ChanStatusReg = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase) +
> + CSP_UART_CSR));
> +
> + *Control = 0;
> +
> + if ((ModemStatusReg & CSP_UART_MSR_CTS) == CSP_UART_MSR_CTS) {
> + *Control |= EFI_SERIAL_CLEAR_TO_SEND;
> + }
> +
> + if ((ModemStatusReg & CSP_UART_MSR_DSR) == CSP_UART_MSR_DSR) {
> + *Control |= EFI_SERIAL_DATA_SET_READY;
> + }
> +
> + if ((ModemStatusReg & CSP_UART_MSR_RI) == CSP_UART_MSR_RI) {
> + *Control |= EFI_SERIAL_RING_INDICATE;
> + }
> +
> + if ((ModemStatusReg & CSP_UART_MSR_DCD) == CSP_UART_MSR_DCD) {
> + *Control |= EFI_SERIAL_CARRIER_DETECT;
> + }
> +
> + if ((ModemCtrlReg & CSP_UART_MCR_RTS) == CSP_UART_MCR_RTS) {
> + *Control |= EFI_SERIAL_REQUEST_TO_SEND;
> + }
> +
> + if ((ModemCtrlReg & CSP_UART_MCR_DTR) == CSP_UART_MCR_DTR) {
> + *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
> + }
> +
> + if ((ChanStatusReg & CSP_UART_CSR_REMPTY) == CSP_UART_CSR_REMPTY) {
> + *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
> + }
> +
> + if ((ChanStatusReg & CSP_UART_CSR_TEMPTY) == CSP_UART_CSR_TEMPTY) {
> + *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
> + }
> +
> + if ((ModemCtrlReg & CSP_UART_MCR_FCM) == CSP_UART_MCR_FCM) {
> + *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
> + }
> +
> + return RETURN_SUCCESS;
> +}
> +
> +
> +/**
> +
> + Initialise the serial port to the specified settings.
> + The serial port is re-configured only if the specified settings
> + are different from the current settings.
> + All unspecified settings will be set to the default values.
> +
> + @param UartBase The base address of the serial device.
> + @param BaudRate The baud rate of the serial device. If the
> + baud rate is not supported, the speed will be
> + reduced to the nearest supported one and the
> + variable's value will be updated accordingly.
> + @param Parity If applicable, this is the EFI_PARITY_TYPE
> + that is computed or checked as each character
> + is transmitted or received. If the device
> + does not support parity, the value is the
> + default parity value.
> + @param DataBits The number of data bits in each character.
> + @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
> + of stop bits per character.
> + If the device does not support stop bits, the
> + value is the default stop bit value.
> +
> + @retval RETURN_SUCCESS All attributes were set correctly on the
> + serial device.
> + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an
> + unsupported value.
> +
> +**/
> +RETURN_STATUS
> +EFIAPI
> +CspUartInitializePort (
> + IN UINTN UartBase,
> + IN OUT UINT64 *BaudRate,
> + IN OUT EFI_PARITY_TYPE *Parity,
> + IN OUT UINT8 *DataBits,
> + IN OUT EFI_STOP_BITS_TYPE *StopBits
> + )
> +{
> + UINT32 RegVal = 0;
> + UINT32 BaudDivisor = 0;
> +
> + // Wait for Tx FIFO to empty before initializing
> + if (!(MmioRead32 (UartBase + CSP_UART_CR) & CSP_UART_CR_TXDIS)) {
> + while (!(MmioRead32 (UartBase + CSP_UART_CSR) & CSP_UART_CSR_TEMPTY))
> + ;
> + }
> +
> + // Disable Tx/Rx before setting baud rate
> + RegVal = MmioRead32 (UartBase + CSP_UART_CR);
> + RegVal |= CSP_UART_CR_TXDIS | CSP_UART_CR_RXDIS;
> + MmioWrite32 ((UartBase + CSP_UART_CR), RegVal);
> +
> + // Set baud rate
> + UINT32 SelClk = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSysRegBase) +
> + CSP_SYSREG_CPU_FREQ));
> + UINT32 BDiv = 0;
> +
> + if (SelClk < 0x1800000) {
> + BaudDivisor = 1;
> + } else {
> + BaudDivisor = 8;
> + }
> + MmioWrite32 ((UartBase + CSP_UART_BRGR), BaudDivisor);
> + BDiv = (SelClk + ((*BaudRate * BaudDivisor) / 2)) / (*BaudRate * BaudDivisor);
> + MmioWrite32 ((UartBase + CSP_UART_BDIV), (BDiv - 1));
> +
> + // Reset and enable Tx/Rx
> + RegVal = MmioRead32 (UartBase + CSP_UART_CR);
> + RegVal &= ~(CSP_UART_CR_TXDIS | CSP_UART_CR_RXDIS);
> + RegVal |= CSP_UART_CR_TXEN | CSP_UART_CR_TXRES | \
> + CSP_UART_CR_RXEN | CSP_UART_CR_RXRES;;
> + MmioWrite32 ((UartBase + CSP_UART_CR), RegVal);
> +
> + RegVal = MmioRead32 (UartBase + CSP_UART_MR) & 1;
> +
> + //
> + // Data Bits
> + //
> + switch (*DataBits) {
> + case 0:
> + *DataBits = 8;
> + case 8:
> + RegVal |= CSP_UART_MR_CHRL_8;
> + break;
> + case 7:
> + RegVal |= CSP_UART_MR_CHRL_7;
> + break;
> + case 6:
> + RegVal |= CSP_UART_MR_CHRL_6;
> + break;
> + default:
> + return RETURN_INVALID_PARAMETER;
> + }
> +
> + //
> + // Stop Bits
> + //
> + switch (*StopBits) {
> + case DefaultStopBits:
> + *StopBits = OneStopBit;
> + case OneStopBit:
> + RegVal |= CSP_UART_MR_NBSTOP_1;
> + break;
> + case TwoStopBits:
> + RegVal |= CSP_UART_MR_NBSTOP_2;
> + break;
> + default:
> + return RETURN_INVALID_PARAMETER;
> + }
> +
> + //
> + // Parity
> + //
> + switch (*Parity) {
> + case DefaultParity:
> + *Parity = NoParity;
> + case NoParity:
> + RegVal |= CSP_UART_MR_PAR_NONE;
> + break;
> + case EvenParity:
> + RegVal |= CSP_UART_MR_PAR_EVEN;
> + break;
> + case OddParity:
> + RegVal |= CSP_UART_MR_PAR_ODD;
> + break;
> + case MarkParity:
> + RegVal |= CSP_UART_MR_PAR_MARK;
> + break;
> + case SpaceParity:
> + RegVal |= CSP_UART_MR_PAR_SPACE;
> + break;
> + default:
> + return RETURN_INVALID_PARAMETER;
> + }
> +
> + MmioWrite32 ((UartBase + CSP_UART_MR), RegVal);
> +
> + return RETURN_SUCCESS;
> +}
> +
> +VOID CspUartPutChar (IN UINTN UartBase, IN UINT8 Char)
> +{
> + while ((MmioRead32 (UartBase + CSP_UART_CSR) & CSP_UART_CSR_TFUL)
> + == CSP_UART_CSR_TFUL)
> + ;
> + MmioWrite8 (UartBase + CSP_UART_FIFO, Char);
> +}
> +
> +UINT8 CspUartGetChar (IN UINTN UartBase)
> +{
> + while ((MmioRead32 (UartBase + CSP_UART_CSR) & CSP_UART_CSR_REMPTY)
> + == CSP_UART_CSR_REMPTY)
> + ;
> + return MmioRead8 (UartBase + CSP_UART_FIFO);
> +}
> +
> diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
> new file mode 100644
> index 0000000..46ea8f9
> --- /dev/null
> +++ b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
> @@ -0,0 +1,52 @@
> +## @file
> +# Serial Port Library for Cadence IP6528 UART.
> +#
> +# Based on:
> +#
> +# Null instance of Serial Port Library with empty functions.
> +#
> +# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
> +# Copyright (C) 2017 Cadence Design Systems. All rights reserved worldwide.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php.
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 1.25
> + BASE_NAME = CspSerialPortLib
> + MODULE_UNI_FILE = CspSerialPortLib.uni
> + FILE_GUID = C456789-8897-411a-91F8-7D7E45837146
> + MODULE_TYPE = BASE
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = SerialPortLib
> +
> +[Sources]
> + CspSerialPortLib.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + CadencePkg/CadenceCspPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + DebugLib
> + IoLib
> + BaseLib
> + PcdLib
> +
> +[FixedPcd]
> + gCadenceCspTokenSpaceGuid.PcdCspSerialBase
> + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
> +
> diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni
> new file mode 100644
> index 0000000000000000000000000000000000000000..60434d42366ee99f53da028381deff21250cfda8
> GIT binary patch
> literal 1622
> zcmc(fL2uJQ5QXQA#D7?&7eK88T#z`CGzKi7juJ<OQ{^NjwUj2vP8<5?3*TGE-cW+X
> z1)<2^-PxHpZ{Cda<GyQMb3D)ZIeTMYt+1tC+GBf!Rd-`fCDt6fv!SgyZP<OpHf5jl
> z+;J{!WfeC$>x>u&mVBL^Vw+=W>=WzR$TExCEFs$|G2g&b#)Vz^Oiw^~3eHP=ZZGWB
> z0mK35m5*3)J0@OCF728%!qS7g*ay_gpA@C)Zh6nKY(3*8`z>hVe28NPuYyPi(~^h<
> z@0?uD*Djn59#SAji5VW(cuJQ$;#T-OEV*acC|k8!D5~_)OT49|bglUbL->joJNe%7
> zsAoCdQ0JW8crVozm`IJ1II(U}#7uYvObWl(?V7%YxIStQIIG)%OX%0uYcb>fd$k2Q
> zg(x*@y_8FxQPop;HhI+}saj9X&8}PG{2iZ%oPO1%Rznjw-NmnW3W(8WPghOThEBZp
> zldU<cwUvMAtBa_<q(5C4?AKdinZkT-Cl78SP_B5woT!rb7Q<)Al&AKNch5d?PSDb!
> zrq&E=Vtt#ii@m}VJ7bNp2ZW%0!Z#4(G4{wQJ59CT9aiBAwZq!?XPu7sYCq>*yi%Xh
> z**RV#&+H6)0;(`lpMAth++|bF3}5*uYwh(GUuFNo`hgoUKV~2AveZ??_PNCg=m}a3
> znJ48O?CBO}O8-S&&s{b>NA1+qUr(*y1xP6v6VPJ2fRXf)vOUzw;Pa>75na?*u%Pof
> rZ_S-%;RGx(?eP9r|9YLavcIcJGcl$f&C9Uu!=cLlXH^lJHQo9N7Zm#w
>
> literal 0
> HcmV?d00001
>
> --
> 2.2.2
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [staging/cadence-aarch64 PATCH v3 2/6] CadencePkg: Add library for Cadence UART.
2017-06-22 15:02 ` Leif Lindholm
@ 2017-06-23 18:38 ` Ard Biesheuvel
0 siblings, 0 replies; 16+ messages in thread
From: Ard Biesheuvel @ 2017-06-23 18:38 UTC (permalink / raw)
To: Leif Lindholm
Cc: Scott Telford, edk2-devel@lists.01.org, Graeme Gregory,
afish@apple.com, Kinney, Michael D
On 22 June 2017 at 15:02, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Thu, Jun 22, 2017 at 10:31:57AM +0100, Scott Telford wrote:
>> Add serial port library to support the Cadence IP6528 UART used in the
>> Cadence CSP platform.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Scott Telford <stelford@cadence.com>
>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>> CadencePkg/Include/Library/CspSerialPortLib.h | 86 ++++
>> .../CadenceCspSerialPortLib/CspSerialPortLib.c | 523 +++++++++++++++++++++
>> .../CadenceCspSerialPortLib/CspSerialPortLib.inf | 52 ++
>> .../CadenceCspSerialPortLib/CspSerialPortLib.uni | Bin 0 -> 1622 bytes
>> 4 files changed, 661 insertions(+)
>> create mode 100644 CadencePkg/Include/Library/CspSerialPortLib.h
>> create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
>> create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
>> create mode 100644 CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni
>>
>> diff --git a/CadencePkg/Include/Library/CspSerialPortLib.h b/CadencePkg/Include/Library/CspSerialPortLib.h
>> new file mode 100644
>> index 0000000..46fa0d8
>> --- /dev/null
>> +++ b/CadencePkg/Include/Library/CspSerialPortLib.h
>> @@ -0,0 +1,86 @@
>> +/** @file
>> +* Serial Port Library for Cadence IP6528 UART.
>> +* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
>> +*
>> +* This program and the accompanying materials are licensed and made
>> +* available under the terms and conditions of the BSD License which
>> +* accompanies this distribution. The full text of the license may be
>> +* found at http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#ifndef __CSP_SERIAL_PORT_LIB_H__
>> +#define __CSP_SERIAL_PORT_LIB_H__
>> +
>> +// Cadence UART register offsets
>> +#define CSP_UART_CR 0x00 // Control
>> +#define CSP_UART_MR 0x04 // Mode
>> +#define CSP_UART_IER 0x08 // Interrupt enable
>> +#define CSP_UART_IDR 0x0C // Interrupt disable
>> +#define CSP_UART_IMR 0x10 // Interrupt mask
>> +#define CSP_UART_CISR 0x14 // Channel interrupt status
>> +#define CSP_UART_BRGR 0x18 // Baud rate generator
>> +#define CSP_UART_RTOR 0x1C // Rx Timeout
>> +#define CSP_UART_RTRIG 0x20 // Rx FIFO trigger level
>> +#define CSP_UART_MCR 0x24 // Modem control
>> +#define CSP_UART_MSR 0x28 // Modem status
>> +#define CSP_UART_CSR 0x2C // Channel status
>> +#define CSP_UART_FIFO 0x30 // FIFO (Tx/Rx)
>> +#define CSP_UART_BDIV 0x34 // Baud rate divider
>> +#define CSP_UART_FDEL 0x38 // Flow delay
>> +#define CSP_UART_PMIN 0x3C // IR min received pulse width
>> +#define CSP_UART_PWID 0x40 // IR transmitted pulse Width
>> +#define CSP_UART_TTRIG 0x44 // Tx FIFO trigger level
>> +
>> +
>> +// Control Register Bit Definitions
>> +#define CSP_UART_CR_STPBRK 0x00000100 // Stop Tx break
>> +#define CSP_UART_CR_STTBRK 0x00000080 // Start Tx break
>> +#define CSP_UART_CR_RSTTO 0x00000040 // Restart Rx timeout Counter
>> +#define CSP_UART_CR_TXDIS 0x00000020 // Tx disable
>> +#define CSP_UART_CR_TXEN 0x00000010 // Tx enable
>> +#define CSP_UART_CR_RXDIS 0x00000008 // Rx disable
>> +#define CSP_UART_CR_RXEN 0x00000004 // Rx enable
>> +#define CSP_UART_CR_TXRES 0x00000002 // Tx reset
>> +#define CSP_UART_CR_RXRES 0x00000001 // Rx reset
>> +
>> +
>> +// Mode register bit definitions
>> +#define CSP_UART_MR_CLKS 0x00000001 // Baud rate /8 pre-scalar
>> +#define CSP_UART_MR_CHMODE_LLB 0x00000200 // Local loopback mode
>> +#define CSP_UART_MR_CHMODE_NML 0x00000000 // Normal mode
>> +
>> +#define CSP_UART_MR_CHRL_6 0x00000006 // 6 databits
>> +#define CSP_UART_MR_CHRL_7 0x00000004 // 7 databits
>> +#define CSP_UART_MR_CHRL_8 0x00000000 // 8 databits
>> +
>> +#define CSP_UART_MR_PAR_NONE 0x00000020 // No parity mode
>> +#define CSP_UART_MR_PAR_MARK 0x00000018 // Mark parity mode
>> +#define CSP_UART_MR_PAR_SPACE 0x00000010 // Space parity mode
>> +#define CSP_UART_MR_PAR_ODD 0x00000008 // Odd parity mode
>> +#define CSP_UART_MR_PAR_EVEN 0x00000000 // Even parity mode
>> +
>> +#define CSP_UART_MR_NBSTOP_1 0x00000000 // 1 stop bit
>> +#define CSP_UART_MR_NBSTOP_2 0x00000080 // 2 stop bits
>> +
>> +// Modem control register bit definitions
>> +#define CSP_UART_MCR_DTR 0x00000001 // DTR control
>> +#define CSP_UART_MCR_RTS 0x00000002 // RTS control
>> +#define CSP_UART_MCR_FCM 0x00000020 // Auto flow control
>> +
>> +// Modem status register bit definitions
>> +#define CSP_UART_MSR_FCMS 0x00000100 // Auto flow control status
>> +#define CSP_UART_MSR_DCD 0x00000080 // DCD status
>> +#define CSP_UART_MSR_RI 0x00000040 // RI status
>> +#define CSP_UART_MSR_DSR 0x00000020 // DSR status
>> +#define CSP_UART_MSR_CTS 0x00000010 // CTS status
>> +
>> +// Channel status register bit definitions
>> +#define CSP_UART_CSR_REMPTY 0x00000002 // Rx FIFO empty
>> +#define CSP_UART_CSR_TEMPTY 0x00000008 // Tx FIFO empty
>> +#define CSP_UART_CSR_TFUL 0x00000010 // Tx FIFO full
>> +
>> +#endif
>> diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
>> new file mode 100644
>> index 0000000..9a9e14a
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.c
>> @@ -0,0 +1,523 @@
>> +/** @file
>> + Serial Port Library for Cadence IP6528 UART.
>> + Copyright (c) 2015-2017, Cadence Design Systems, Inc. All rights reserved.
>> +
>> + Based on:
>> +
>> + Null Serial Port library instance with empty functions.
>> +
>> + Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
>> + This program and the accompanying materials
>> + are licensed and made available under the terms and conditions of the BSD License
>> + which accompanies this distribution. The full text of the license may be found at
>> + http://opensource.org/licenses/bsd-license.php.
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +
>> +**/
>> +
>> +#include <Base.h>
>> +#include <Library/BaseLib.h>
>> +#include <Library/CspSerialPortLib.h>
>> +#include <Library/CspSysReg.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PcdLib.h>
>> +#include <Library/SerialPortLib.h>
>> +
>> +
>> +RETURN_STATUS
>> +EFIAPI
>> +CspUartInitializePort (
>> + IN UINTN UartBase,
>> + IN OUT UINT64 *BaudRate,
>> + IN OUT EFI_PARITY_TYPE *Parity,
>> + IN OUT UINT8 *DataBits,
>> + IN OUT EFI_STOP_BITS_TYPE *StopBits
>> +);
>> +VOID CspUartPutChar (IN UINTN UartBase, IN UINT8 Char);
>> +UINT8 CspUartGetChar (IN UINTN UartBase);
>> +
>> +/**
>> + Initialize the serial device hardware.
>> +
>> + If no initialization is required, then return RETURN_SUCCESS.
>> + If the serial device was successfully initialized, then return RETURN_SUCCESS.
>> + If the serial device could not be initialized, then return RETURN_DEVICE_ERROR.
>> +
>> + @retval RETURN_SUCCESS The serial device was initialized.
>> + @retval RETURN_DEVICE_ERROR The serial device could not be initialized.
>> +
>> +**/
>> +RETURN_STATUS
>> +EFIAPI
>> +SerialPortInitialize (
>> + VOID
>> + )
>> +{
>> + UINT64 BaudRate;
>> + EFI_PARITY_TYPE Parity;
>> + UINT8 DataBits;
>> + EFI_STOP_BITS_TYPE StopBits;
>> +
>> + BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
>> + Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
>> + DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
>> + StopBits = (EFI_STOP_BITS_TYPE)FixedPcdGet8 (PcdUartDefaultStopBits);
>> +
>> + return CspUartInitializePort (
>> + (UINTN)FixedPcdGet64 (PcdCspSerialBase),
>> + &BaudRate,
>> + &Parity,
>> + &DataBits,
>> + &StopBits
>> + );
>> +}
>> +
>> +/**
>> + Set new attributes to UART.
>> +
>> + @param BaudRate The baud rate of the serial device. If the
>> + baud rate is not supported, the speed will
>> + be reduced down to the nearest supported one
>> + and the variable's value will be updated
>> + accordingly.
>> + @param ReceiveFifoDepth The number of characters the device will
>> + buffer on input. If the specified value is
>> + not supported, the variable's value will
>> + be reduced down to the nearest supported one.
>> + @param Timeout If applicable, the number of microseconds the
>> + device will wait before timing out a Read or
>> + a Write operation.
>> + @param Parity If applicable, this is the EFI_PARITY_TYPE
>> + that is computed or checked as each character
>> + is transmitted or received. If the device
>> + does not support parity, the value is the
>> + default parity value.
>> + @param DataBits The number of data bits in each character
>> + @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
>> + of stop bits per character. If the device
>> + does not support stop bits, the value is the
>> + default stop bit value.
>> +
>> + @retval EFI_SUCCESS All attributes were set correctly.
>> + @retval EFI_INVALID_PARAMETERS One or more attributes has an unsupported
>> + value.
>> +
>> +**/
>> +RETURN_STATUS
>> +EFIAPI
>> +SerialPortSetAttributes (
>> + IN OUT UINT64 *BaudRate,
>> + IN OUT UINT32 *ReceiveFifoDepth,
>> + IN OUT UINT32 *Timeout,
>> + IN OUT EFI_PARITY_TYPE *Parity,
>> + IN OUT UINT8 *DataBits,
>> + IN OUT EFI_STOP_BITS_TYPE *StopBits
>> + )
>> +{
>> + return CspUartInitializePort (
>> + (UINTN)FixedPcdGet64 (PcdCspSerialBase),
>> + BaudRate,
>> + Parity,
>> + DataBits,
>> + StopBits
>> + );
>> +}
>> +
>> +/**
>> + Write data from buffer to serial device.
>> +
>> + Writes NumberOfBytes data bytes from Buffer to the serial device.
>> + The number of bytes actually written to the serial device is returned.
>> + If the return value is less than NumberOfBytes, then the write operation failed.
>> + If Buffer is NULL, then ASSERT().
>> + If NumberOfBytes is zero, then return 0.
>> +
>> + @param Buffer The pointer to the data buffer to be written.
>> + @param NumberOfBytes The number of bytes to written to the serial device.
>> +
>> + @retval 0 NumberOfBytes is 0.
>> + @retval >0 The number of bytes written to the serial device.
>> + If this value is less than NumberOfBytes, then the read operation failed.
>> +
>> +**/
>> +UINTN
>> +EFIAPI
>> +SerialPortWrite (
>> + IN UINT8 *Buffer,
>> + IN UINTN NumberOfBytes
>> +)
>> +{
>> + UINTN i;
>> + for (i = 0; i < NumberOfBytes; i++) {
>> + CspUartPutChar ((UINTN)PcdGet64 (PcdCspSerialBase), Buffer[i]);
>> + }
>> + return i;
>> +}
>> +
>> +
>> +/**
>> + Read data from serial device and save the datas in buffer.
>> +
>> + Reads NumberOfBytes data bytes from a serial device into the buffer
>> + specified by Buffer. The number of bytes actually read is returned.
>> + If the return value is less than NumberOfBytes, then the rest operation failed.
>> + If Buffer is NULL, then ASSERT().
>> + If NumberOfBytes is zero, then return 0.
>> +
>> + @param Buffer The pointer to the data buffer to store the data read from the serial device.
>> + @param NumberOfBytes The number of bytes which will be read.
>> +
>> + @retval 0 Read data failed; No data is to be read.
>> + @retval >0 The actual number of bytes read from serial device.
>> +
>> +**/
>> +UINTN
>> +EFIAPI
>> +SerialPortRead (
>> + OUT UINT8 *Buffer,
>> + IN UINTN NumberOfBytes
>> +)
>> +{
>> + UINTN i;
>> + for (i = 0; i < NumberOfBytes; i++) {
>> + Buffer[i] = CspUartGetChar ((UINTN)PcdGet64 (PcdCspSerialBase));
>> + }
>> + return i;
>> +}
>> +
>> +/**
>> + Polls a serial device to see if there is any data waiting to be read.
>> +
>> + Polls a serial device to see if there is any data waiting to be read.
>> + If there is data waiting to be read from the serial device, then TRUE is returned.
>> + If there is no data waiting to be read from the serial device, then FALSE is returned.
>> +
>> + @retval TRUE Data is waiting to be read from the serial device.
>> + @retval FALSE There is no data waiting to be read from the serial device.
>> +
>> +**/
>> +BOOLEAN
>> +EFIAPI
>> +SerialPortPoll (
>> + VOID
>> + )
>> +{
>> + return (MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase + CSP_UART_CSR))) &
>> + CSP_UART_CSR_REMPTY) ? FALSE : TRUE;
>> +}
>> +
>> +/**
>> +
>> + Assert or deassert the control signals on a serial port.
>> + The following control signals are set according their bit settings :
>> + . Request to Send
>> + . Data Terminal Ready
>> +
>> + @param[in] Control The following bits are taken into account :
>> + . EFI_SERIAL_REQUEST_TO_SEND : assert/deassert the
>> + "Request To Send" control signal if this bit is
>> + equal to one/zero.
>> + . EFI_SERIAL_DATA_TERMINAL_READY : assert/deassert
>> + the "Data Terminal Ready" control signal if this
>> + bit is equal to one/zero.
>> + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : enable/disable
>> + the hardware loopback if this bit is equal to
>> + one/zero.
>> + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : not supported.
>> + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : enable/
>> + disable the hardware flow control based on CTS (Clear
>> + To Send) and RTS (Ready To Send) control signals.
>> +
>> + @retval RETURN_SUCCESS The new control bits were set on the device.
>> + @retval RETURN_UNSUPPORTED The device does not support this operation.
>> +
>> +**/
>> +RETURN_STATUS
>> +EFIAPI
>> +SerialPortSetControl (
>> + IN UINT32 Control
>> + )
>> +{
>> + UINT32 Bits;
>> +
>> + if (Control & (EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE |
>> + EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE )) {
>> + return RETURN_UNSUPPORTED;
>> + }
>> +
>> + Bits = MmioRead32 (PcdGet64 (PcdCspSerialBase) + CSP_UART_MCR);
>> +
>> + if (Control & EFI_SERIAL_REQUEST_TO_SEND) {
>> + Bits |= CSP_UART_MCR_RTS;
>> + } else {
>> + Bits &= ~CSP_UART_MCR_RTS;
>> + }
>> +
>> + if (Control & EFI_SERIAL_DATA_TERMINAL_READY) {
>> + Bits |= CSP_UART_MCR_DTR;
>> + } else {
>> + Bits &= ~CSP_UART_MCR_DTR;
>> + }
>> +
>> + if (Control & EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE) {
>> + Bits |= CSP_UART_MCR_FCM;
>> + } else {
>> + Bits &= CSP_UART_MCR_FCM;
>> + }
>> +
>> + MmioWrite32 ((PcdGet64 (PcdCspSerialBase) + CSP_UART_MCR), Bits);
>> +
>> + return RETURN_SUCCESS;
>> +}
>> +
>> +/**
>> +
>> + Retrieve the status of the control bits on a serial device.
>> +
>> + @param[out] Control Status of the control bits on a serial device :
>> +
>> + . EFI_SERIAL_DATA_CLEAR_TO_SEND,
>> + EFI_SERIAL_DATA_SET_READY,
>> + EFI_SERIAL_RING_INDICATE,
>> + EFI_SERIAL_CARRIER_DETECT,
>> + EFI_SERIAL_REQUEST_TO_SEND,
>> + EFI_SERIAL_DATA_TERMINAL_READY
>> + are all related to the DTE (Data Terminal Equipment)
>> + and DCE (Data Communication Equipment) modes of
>> + operation of the serial device.
>> + . EFI_SERIAL_INPUT_BUFFER_EMPTY : equal to one if the
>> + receive buffer is empty, 0 otherwise.
>> + . EFI_SERIAL_OUTPUT_BUFFER_EMPTY : equal to one if the
>> + transmit buffer is empty, 0 otherwise.
>> + . EFI_SERIAL_HARDWARE_LOOPBACK_ENABLE : equal to one if
>> + the hardware loopback is enabled (the output feeds
>> + the receive buffer), 0 otherwise.
>> + . EFI_SERIAL_SOFTWARE_LOOPBACK_ENABLE : equal to one
>> + if a loopback is accomplished by software, else 0.
>> + . EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE : equal to
>> + one if the hardware flow control based on CTS (Clear
>> + To Send) and RTS (Ready To Send) control signals is
>> + enabled, 0 otherwise.
>> +
>> + @retval RETURN_SUCCESS The control bits were read from the device.
>> +
>> +**/
>> +RETURN_STATUS
>> +EFIAPI
>> +SerialPortGetControl (
>> + OUT UINT32 *Control
>> + )
>> +{
>> + UINT32 ModemStatusReg;
>> + UINT32 ModemCtrlReg;
>> + UINT32 ChanStatusReg;
>> +
>> + ModemCtrlReg = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase) +
>> + CSP_UART_MCR));
>> + ModemStatusReg = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase) +
>> + CSP_UART_MSR));
>> + ChanStatusReg = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSerialBase) +
>> + CSP_UART_CSR));
>> +
>> + *Control = 0;
>> +
>> + if ((ModemStatusReg & CSP_UART_MSR_CTS) == CSP_UART_MSR_CTS) {
>> + *Control |= EFI_SERIAL_CLEAR_TO_SEND;
>> + }
>> +
>> + if ((ModemStatusReg & CSP_UART_MSR_DSR) == CSP_UART_MSR_DSR) {
>> + *Control |= EFI_SERIAL_DATA_SET_READY;
>> + }
>> +
>> + if ((ModemStatusReg & CSP_UART_MSR_RI) == CSP_UART_MSR_RI) {
>> + *Control |= EFI_SERIAL_RING_INDICATE;
>> + }
>> +
>> + if ((ModemStatusReg & CSP_UART_MSR_DCD) == CSP_UART_MSR_DCD) {
>> + *Control |= EFI_SERIAL_CARRIER_DETECT;
>> + }
>> +
>> + if ((ModemCtrlReg & CSP_UART_MCR_RTS) == CSP_UART_MCR_RTS) {
>> + *Control |= EFI_SERIAL_REQUEST_TO_SEND;
>> + }
>> +
>> + if ((ModemCtrlReg & CSP_UART_MCR_DTR) == CSP_UART_MCR_DTR) {
>> + *Control |= EFI_SERIAL_DATA_TERMINAL_READY;
>> + }
>> +
>> + if ((ChanStatusReg & CSP_UART_CSR_REMPTY) == CSP_UART_CSR_REMPTY) {
>> + *Control |= EFI_SERIAL_INPUT_BUFFER_EMPTY;
>> + }
>> +
>> + if ((ChanStatusReg & CSP_UART_CSR_TEMPTY) == CSP_UART_CSR_TEMPTY) {
>> + *Control |= EFI_SERIAL_OUTPUT_BUFFER_EMPTY;
>> + }
>> +
>> + if ((ModemCtrlReg & CSP_UART_MCR_FCM) == CSP_UART_MCR_FCM) {
>> + *Control |= EFI_SERIAL_HARDWARE_FLOW_CONTROL_ENABLE;
>> + }
>> +
>> + return RETURN_SUCCESS;
>> +}
>> +
>> +
>> +/**
>> +
>> + Initialise the serial port to the specified settings.
>> + The serial port is re-configured only if the specified settings
>> + are different from the current settings.
>> + All unspecified settings will be set to the default values.
>> +
>> + @param UartBase The base address of the serial device.
>> + @param BaudRate The baud rate of the serial device. If the
>> + baud rate is not supported, the speed will be
>> + reduced to the nearest supported one and the
>> + variable's value will be updated accordingly.
>> + @param Parity If applicable, this is the EFI_PARITY_TYPE
>> + that is computed or checked as each character
>> + is transmitted or received. If the device
>> + does not support parity, the value is the
>> + default parity value.
>> + @param DataBits The number of data bits in each character.
>> + @param StopBits If applicable, the EFI_STOP_BITS_TYPE number
>> + of stop bits per character.
>> + If the device does not support stop bits, the
>> + value is the default stop bit value.
>> +
>> + @retval RETURN_SUCCESS All attributes were set correctly on the
>> + serial device.
>> + @retval RETURN_INVALID_PARAMETER One or more of the attributes has an
>> + unsupported value.
>> +
>> +**/
>> +RETURN_STATUS
>> +EFIAPI
>> +CspUartInitializePort (
>> + IN UINTN UartBase,
>> + IN OUT UINT64 *BaudRate,
>> + IN OUT EFI_PARITY_TYPE *Parity,
>> + IN OUT UINT8 *DataBits,
>> + IN OUT EFI_STOP_BITS_TYPE *StopBits
>> + )
>> +{
>> + UINT32 RegVal = 0;
>> + UINT32 BaudDivisor = 0;
>> +
>> + // Wait for Tx FIFO to empty before initializing
>> + if (!(MmioRead32 (UartBase + CSP_UART_CR) & CSP_UART_CR_TXDIS)) {
>> + while (!(MmioRead32 (UartBase + CSP_UART_CSR) & CSP_UART_CSR_TEMPTY))
>> + ;
>> + }
>> +
>> + // Disable Tx/Rx before setting baud rate
>> + RegVal = MmioRead32 (UartBase + CSP_UART_CR);
>> + RegVal |= CSP_UART_CR_TXDIS | CSP_UART_CR_RXDIS;
>> + MmioWrite32 ((UartBase + CSP_UART_CR), RegVal);
>> +
>> + // Set baud rate
>> + UINT32 SelClk = MmioRead32 ((UINTN)(PcdGet64 (PcdCspSysRegBase) +
>> + CSP_SYSREG_CPU_FREQ));
>> + UINT32 BDiv = 0;
>> +
>> + if (SelClk < 0x1800000) {
>> + BaudDivisor = 1;
>> + } else {
>> + BaudDivisor = 8;
>> + }
>> + MmioWrite32 ((UartBase + CSP_UART_BRGR), BaudDivisor);
>> + BDiv = (SelClk + ((*BaudRate * BaudDivisor) / 2)) / (*BaudRate * BaudDivisor);
>> + MmioWrite32 ((UartBase + CSP_UART_BDIV), (BDiv - 1));
>> +
>> + // Reset and enable Tx/Rx
>> + RegVal = MmioRead32 (UartBase + CSP_UART_CR);
>> + RegVal &= ~(CSP_UART_CR_TXDIS | CSP_UART_CR_RXDIS);
>> + RegVal |= CSP_UART_CR_TXEN | CSP_UART_CR_TXRES | \
>> + CSP_UART_CR_RXEN | CSP_UART_CR_RXRES;;
>> + MmioWrite32 ((UartBase + CSP_UART_CR), RegVal);
>> +
>> + RegVal = MmioRead32 (UartBase + CSP_UART_MR) & 1;
>> +
>> + //
>> + // Data Bits
>> + //
>> + switch (*DataBits) {
>> + case 0:
>> + *DataBits = 8;
>> + case 8:
>> + RegVal |= CSP_UART_MR_CHRL_8;
>> + break;
>> + case 7:
>> + RegVal |= CSP_UART_MR_CHRL_7;
>> + break;
>> + case 6:
>> + RegVal |= CSP_UART_MR_CHRL_6;
>> + break;
>> + default:
>> + return RETURN_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // Stop Bits
>> + //
>> + switch (*StopBits) {
>> + case DefaultStopBits:
>> + *StopBits = OneStopBit;
>> + case OneStopBit:
>> + RegVal |= CSP_UART_MR_NBSTOP_1;
>> + break;
>> + case TwoStopBits:
>> + RegVal |= CSP_UART_MR_NBSTOP_2;
>> + break;
>> + default:
>> + return RETURN_INVALID_PARAMETER;
>> + }
>> +
>> + //
>> + // Parity
>> + //
>> + switch (*Parity) {
>> + case DefaultParity:
>> + *Parity = NoParity;
>> + case NoParity:
>> + RegVal |= CSP_UART_MR_PAR_NONE;
>> + break;
>> + case EvenParity:
>> + RegVal |= CSP_UART_MR_PAR_EVEN;
>> + break;
>> + case OddParity:
>> + RegVal |= CSP_UART_MR_PAR_ODD;
>> + break;
>> + case MarkParity:
>> + RegVal |= CSP_UART_MR_PAR_MARK;
>> + break;
>> + case SpaceParity:
>> + RegVal |= CSP_UART_MR_PAR_SPACE;
>> + break;
>> + default:
>> + return RETURN_INVALID_PARAMETER;
>> + }
>> +
>> + MmioWrite32 ((UartBase + CSP_UART_MR), RegVal);
>> +
>> + return RETURN_SUCCESS;
>> +}
>> +
>> +VOID CspUartPutChar (IN UINTN UartBase, IN UINT8 Char)
>> +{
>> + while ((MmioRead32 (UartBase + CSP_UART_CSR) & CSP_UART_CSR_TFUL)
>> + == CSP_UART_CSR_TFUL)
>> + ;
>> + MmioWrite8 (UartBase + CSP_UART_FIFO, Char);
>> +}
>> +
>> +UINT8 CspUartGetChar (IN UINTN UartBase)
>> +{
>> + while ((MmioRead32 (UartBase + CSP_UART_CSR) & CSP_UART_CSR_REMPTY)
>> + == CSP_UART_CSR_REMPTY)
>> + ;
>> + return MmioRead8 (UartBase + CSP_UART_FIFO);
>> +}
>> +
>> diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
>> new file mode 100644
>> index 0000000..46ea8f9
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
>> @@ -0,0 +1,52 @@
>> +## @file
>> +# Serial Port Library for Cadence IP6528 UART.
>> +#
>> +# Based on:
>> +#
>> +# Null instance of Serial Port Library with empty functions.
>> +#
>> +# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.<BR>
>> +# Copyright (C) 2017 Cadence Design Systems. All rights reserved worldwide.
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php.
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 1.25
>> + BASE_NAME = CspSerialPortLib
>> + MODULE_UNI_FILE = CspSerialPortLib.uni
>> + FILE_GUID = C456789-8897-411a-91F8-7D7E45837146
>> + MODULE_TYPE = BASE
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = SerialPortLib
>> +
>> +[Sources]
>> + CspSerialPortLib.c
>> +
>> +[Packages]
>> + ArmPkg/ArmPkg.dec
>> + CadencePkg/CadenceCspPkg.dec
>> + EmbeddedPkg/EmbeddedPkg.dec
>> + MdePkg/MdePkg.dec
>> +
>> +[LibraryClasses]
>> + DebugLib
>> + IoLib
>> + BaseLib
>> + PcdLib
>> +
>> +[FixedPcd]
>> + gCadenceCspTokenSpaceGuid.PcdCspSerialBase
>> + gCadenceCspTokenSpaceGuid.PcdCspSysRegBase
>> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
>> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
>> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
>> + gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
>> +
>> diff --git a/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni b/CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.uni
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..60434d42366ee99f53da028381deff21250cfda8
>> GIT binary patch
>> literal 1622
>> zcmc(fL2uJQ5QXQA#D7?&7eK88T#z`CGzKi7juJ<OQ{^NjwUj2vP8<5?3*TGE-cW+X
>> z1)<2^-PxHpZ{Cda<GyQMb3D)ZIeTMYt+1tC+GBf!Rd-`fCDt6fv!SgyZP<OpHf5jl
>> z+;J{!WfeC$>x>u&mVBL^Vw+=W>=WzR$TExCEFs$|G2g&b#)Vz^Oiw^~3eHP=ZZGWB
>> z0mK35m5*3)J0@OCF728%!qS7g*ay_gpA@C)Zh6nKY(3*8`z>hVe28NPuYyPi(~^h<
>> z@0?uD*Djn59#SAji5VW(cuJQ$;#T-OEV*acC|k8!D5~_)OT49|bglUbL->joJNe%7
>> zsAoCdQ0JW8crVozm`IJ1II(U}#7uYvObWl(?V7%YxIStQIIG)%OX%0uYcb>fd$k2Q
>> zg(x*@y_8FxQPop;HhI+}saj9X&8}PG{2iZ%oPO1%Rznjw-NmnW3W(8WPghOThEBZp
>> zldU<cwUvMAtBa_<q(5C4?AKdinZkT-Cl78SP_B5woT!rb7Q<)Al&AKNch5d?PSDb!
>> zrq&E=Vtt#ii@m}VJ7bNp2ZW%0!Z#4(G4{wQJ59CT9aiBAwZq!?XPu7sYCq>*yi%Xh
>> z**RV#&+H6)0;(`lpMAth++|bF3}5*uYwh(GUuFNo`hgoUKV~2AveZ??_PNCg=m}a3
>> znJ48O?CBO}O8-S&&s{b>NA1+qUr(*y1xP6v6VPJ2fRXf)vOUzw;Pa>75na?*u%Pof
>> rZ_S-%;RGx(?eP9r|9YLavcIcJGcl$f&C9Uu!=cLlXH^lJHQo9N7Zm#w
>>
>> literal 0
>> HcmV?d00001
>>
>> --
>> 2.2.2
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [staging/cadence-aarch64 PATCH v3 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex.
2017-06-22 9:31 [staging/cadence-aarch64 PATCH v3 0/6] CadencePkg: Add package for Cadence hardware IP support Scott Telford
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 1/6] CadencePkg: Add libraries for Cadence CSP platform Scott Telford
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 2/6] CadencePkg: Add library for Cadence UART Scott Telford
@ 2017-06-22 9:31 ` Scott Telford
2017-06-22 15:12 ` Leif Lindholm
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform Scott Telford
` (2 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Scott Telford @ 2017-06-22 9:31 UTC (permalink / raw)
To: edk2-devel, leif.lindholm, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex.
This library is derived from
Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford <stelford@cadence.com>
---
.../Library/CadencePciHostBridgeLib/CdnsPci.c | 149 ++++++++++++++++
.../Library/CadencePciHostBridgeLib/CdnsPci.h | 88 ++++++++++
.../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 188 +++++++++++++++++++++
.../CdnsPciHostBridgeLib.inf | 73 ++++++++
4 files changed, 498 insertions(+)
create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
new file mode 100644
index 0000000..3114843
--- /dev/null
+++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
@@ -0,0 +1,149 @@
+/** @file
+* Initialize the Cadence PCIe Root complex
+*
+* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/BaseLib.h>
+#include <Library/CspSysReg.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/Cpu.h>
+
+#include "CdnsPci.h"
+
+STATIC
+VOID
+CdnsPciConfigRegion (
+ EFI_CPU_IO2_PROTOCOL *CpuIo,
+ IN UINT32 Region,
+ IN UINT32 Descriptor,
+ IN UINT32 TransAddr,
+ IN UINT32 TransAddrBits,
+ IN UINT32 BaseAddr,
+ IN UINT32 BaseAddrBits
+ )
+{
+ UINTN RegionBaseAddr = PCIE_AXI + (Region * PCIE_AXI_REGION_OFF);
+
+ PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_TRANS0_OFF,
+ TransAddr | TransAddrBits);
+ PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_DESC_OFF,
+ Descriptor);
+ PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_BASE0_OFF,
+ BaseAddr | BaseAddrBits);
+}
+
+STATIC
+VOID
+CdnsPciRegInit(
+ EFI_CPU_IO2_PROTOCOL *CpuIo
+)
+{
+ UINT32 Value;
+
+ // Setup the class code as PCIe Host Bridge.
+ PCIE_ROOTPORT_WRITE32 (PCIE_RP + PCIE_PCI_CLASSCODE, PCIE_BRIDGE_CLASSCODE);
+
+ // Set up the BARs via the Root Port registers
+ PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value);
+ PCIE_ROOTPORT_WRITE32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value | (1 << PCIE_RCBARPIE));
+
+ // Allow incoming writes
+ PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR0_IB, PCIE_AXI_BITS_32);
+ PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR1_IB, PCIE_AXI_BITS_32);
+ PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_NO_BAR_IB, PCIE_AXI_BITS_32);
+
+ // Set up region 0 for Type 0 write (bus 0 and 1), size 2MB
+ CdnsPciConfigRegion (
+ CpuIo,
+ 0,
+ PCIE_AXI_DESC_TYPE0,
+ PCIE_ECAM_BASE,
+ PCIE_AXI_BITS_25,
+ 0,
+ PCIE_AXI_BITS_21
+ );
+
+ // Set up region 1 for Type 1 writes (bus 2 upwards), size (32-2)MB
+ CdnsPciConfigRegion(
+ CpuIo,
+ 1,
+ PCIE_AXI_DESC_TYPE1,
+ PCIE_ECAM_BASE + (2*PCIE_BUS_SIZE),
+ PCIE_AXI_BITS_25,
+ 2*PCIE_BUS_SIZE,
+ PCIE_AXI_BITS_25
+ );
+
+ // Set up region 2 for memory write, size 16MB
+ CdnsPciConfigRegion(
+ CpuIo,
+ 2,
+ PCIE_AXI_DESC_MEM,
+ PCIE_MEM32_BASE,
+ PCIE_AXI_BITS_25,
+ (PCIE_MEM32_BASE - PCIE_ECAM_BASE),
+ PCIE_AXI_BITS_24
+ );
+
+ // Set up region 3 for IO write, size 16MB
+ CdnsPciConfigRegion(
+ CpuIo,
+ 3,
+ PCIE_AXI_DESC_IO,
+ PCIE_IO_BASE,
+ PCIE_AXI_BITS_25,
+ (PCIE_IO_BASE - PCIE_ECAM_BASE),
+ PCIE_AXI_BITS_24
+ );
+}
+
+EFI_STATUS
+HWPciRbInit (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ UINT32 Count;
+ EFI_CPU_IO2_PROTOCOL *CpuIo;
+ EFI_STATUS Status;
+ UINT32 Value;
+
+ PCI_TRACE ("HWPciRbInit()");
+
+ PCI_TRACE ("PCIe Setting up Address Translation");
+
+ Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL,
+ (VOID **)&CpuIo);
+ ASSERT_EFI_ERROR (Status);
+
+ // Check for link up
+ for (Count = 0; Count < PCIE_LINK_TIMEOUT_COUNT; Count++) {
+ gBS->Stall (PCIE_LINK_TIMEOUT_WAIT_US);
+ PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_LINK_CTRL_STATUS, Value);
+ if (Value & PCIE_LINK_UP) {
+ break;
+ }
+ }
+ if (!(Value & PCIE_LINK_UP)) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not up: %x.\n", Value));
+ return EFI_NOT_READY;
+ }
+
+ // Initialise configuration registers
+ CdnsPciRegInit(CpuIo);
+
+ return EFI_SUCCESS;
+}
diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
new file mode 100644
index 0000000..08faece
--- /dev/null
+++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
@@ -0,0 +1,88 @@
+/** @file
+* Header for Cadence PCIe Root Complex
+*
+* Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __CDNS_PCI_H__
+#define __CDNS_PCI_H__
+
+#include <Protocol/CpuIo2.h>
+
+#define PCIE_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress)
+#define PCIE_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize)
+#define PCIE_IO_BASE (FixedPcdGet64(PcdPciIoTranslation) + FixedPcdGet64 (PcdPciIoBase))
+#define PCIE_IO_SIZE FixedPcdGet64 (PcdPciIoSize)
+#define PCIE_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base)
+#define PCIE_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size)
+
+#define PCIE_BUS_SIZE SIZE_1MB
+
+#define PCIE_LINK_TIMEOUT_WAIT_US 1000 // microseconds
+#define PCIE_LINK_TIMEOUT_COUNT 1000
+
+#define PCI_TRACE(txt) DEBUG((DEBUG_VERBOSE, "CDNS_PCI: " txt "\n"))
+
+#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); }
+#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); }
+#ifdef CDNS_B2B
+#define PCIE1_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Value); }
+#define PCIE1_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Val); }
+#endif
+
+/*
+ * PCIe Core Configuration Register offsets
+ */
+
+// Root Port Configuration
+#define PCIE_RP 0x00200000
+#define PCIE_PCI_CLASSCODE 0x8
+
+// Local Management
+#define PCIE_LM 0x00100000
+#define PCIE_LINK_CTRL_STATUS 0x00
+#define PCIE_RP_BAR_CONFIG 0x300
+
+// AXI Configuration
+#define PCIE_AXI 0x00400000
+
+#define PCIE_AXI_REGION_OFF 0x020
+#define PCIE_AXI_REGION_TRANS0_OFF 0x000
+#define PCIE_AXI_REGION_DESC_OFF 0x008
+#define PCIE_AXI_REGION_BASE0_OFF 0x018
+
+#define PCIE_AXI_BAR0_IB 0x800
+#define PCIE_AXI_BAR1_IB 0x808
+#define PCIE_AXI_NO_BAR_IB 0x810
+
+/*
+ * PCIe Core Configuration Register values
+ */
+
+#define PCIE_BRIDGE_CLASSCODE 0x06040000
+#define PCIE_LINK_UP 0x01
+#define PCIE_RCBARPIE 0x19
+
+// AXI Region Address Translation/Base Address bits values
+#define PCIE_AXI_BITS_21 20
+#define PCIE_AXI_BITS_24 23
+#define PCIE_AXI_BITS_25 24
+#define PCIE_AXI_BITS_32 31
+
+// AXI Region Outbound PCIe Descriptor Register values
+#define PCIE_AXI_DESC_TYPE0 0x80000A
+#define PCIE_AXI_DESC_TYPE1 0x80000B
+#define PCIE_AXI_DESC_MEM 0x800002
+#define PCIE_AXI_DESC_IO 0x800006
+
+#endif
diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
new file mode 100644
index 0000000..f58cac3
--- /dev/null
+++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
@@ -0,0 +1,188 @@
+/** @file
+ PCI Host Bridge support for the Cadence PCIe Root Complex
+
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+ Copyright (c) 2017, Cadence Design Systems. All rights reserved.
+
+ This program and the accompanying materials are licensed and made available
+ under the terms and conditions of the BSD License which accompanies this
+ distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
+ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciHostBridgeLib.h>
+
+#include <PiDxe.h>
+
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciRootBridgeIo.h>
+
+#pragma pack(1)
+typedef struct {
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+#pragma pack ()
+
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
+ (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID(0x0A03), // PCI
+ 0
+ }, {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+};
+
+STATIC PCI_ROOT_BRIDGE mRootBridge = {
+ 0, // Segment
+ 0, // Supports
+ 0, // Attributes
+ TRUE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM, // AllocationAttributes
+ {
+ // Bus
+ FixedPcdGet32 (PcdPciBusMin),
+ FixedPcdGet32 (PcdPciBusMax)
+ }, {
+ // Io
+ FixedPcdGet64 (PcdPciIoBase),
+ FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
+ }, {
+ // Mem
+ FixedPcdGet32 (PcdPciMmio32Base),
+ FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1
+ }, {
+ // MemAbove4G
+ MAX_UINT64,
+ 0
+ }, {
+ // PMem
+ MAX_UINT64,
+ 0
+ }, {
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath
+};
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param Count Return the count of root bridge instances.
+
+ @return All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ UINTN *Count
+ )
+{
+ *Count = 1;
+
+ return &mRootBridge;
+}
+
+/**
+ Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
+
+ @param Bridges The root bridge instances array.
+ @param Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ PCI_ROOT_BRIDGE *Bridges,
+ UINTN Count
+ )
+{
+}
+
+#ifndef MDEPKG_NDEBUG
+STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = {
+ L"Mem", L"I/O", L"Bus"
+};
+#endif
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param HostBridgeHandle Handle of the Host Bridge.
+ @param Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the resources
+ for all the root bridges. The resource for each root
+ bridge is terminated with END descriptor and an
+ additional END is appended indicating the end of the
+ entire resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ EFI_HANDLE HostBridgeHandle,
+ VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+ DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType <
+ ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)
+ );
+ DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+ //
+ // Skip the END descriptor for root bridge
+ //
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
new file mode 100644
index 0000000..b17a96c
--- /dev/null
+++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
@@ -0,0 +1,73 @@
+## @file
+# PCI Host Bridge Library instance for Cadence PCIe Root Complex
+#
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2017, Cadence Design Systems. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
+# IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 1.25
+ BASE_NAME = CdnsPciHostBridgeLib
+ FILE_GUID = d92c722c-87f9-4988-843e-dffd6bc8c5e3
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
+ CONSTRUCTOR = HWPciRbInit
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = AARCH64 ARM
+#
+
+[Sources]
+ CdnsPciHostBridgeLib.c
+ CdnsPci.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ CadencePkg/CadenceCspPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ DevicePathLib
+ IoLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+
+[Pcd]
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+ gArmTokenSpaceGuid.PcdPciIoTranslation
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+ gArmTokenSpaceGuid.PcdPciMmio32Translation
+ gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress
+ gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
+ gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize
+
+[Protocols]
+ gEfiCpuIo2ProtocolGuid ## CONSUMES
+
+[Depex]
+ gEfiCpuIo2ProtocolGuid
--
2.2.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [staging/cadence-aarch64 PATCH v3 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex.
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex Scott Telford
@ 2017-06-22 15:12 ` Leif Lindholm
2017-06-23 18:43 ` Ard Biesheuvel
0 siblings, 1 reply; 16+ messages in thread
From: Leif Lindholm @ 2017-06-22 15:12 UTC (permalink / raw)
To: Scott Telford
Cc: edk2-devel, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
On Thu, Jun 22, 2017 at 10:31:58AM +0100, Scott Telford wrote:
> Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex.
> This library is derived from
> Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford <stelford@cadence.com>
> ---
> .../Library/CadencePciHostBridgeLib/CdnsPci.c | 149 ++++++++++++++++
> .../Library/CadencePciHostBridgeLib/CdnsPci.h | 88 ++++++++++
> .../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 188 +++++++++++++++++++++
> .../CdnsPciHostBridgeLib.inf | 73 ++++++++
> 4 files changed, 498 insertions(+)
> create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
> create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
> create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
> create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
>
> diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
> new file mode 100644
> index 0000000..3114843
> --- /dev/null
> +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
> @@ -0,0 +1,149 @@
> +/** @file
> +* Initialize the Cadence PCIe Root complex
> +*
> +* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Library/BaseLib.h>
> +#include <Library/CspSysReg.h>
> +#include <Library/DebugLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +
> +#include <Protocol/Cpu.h>
> +
> +#include "CdnsPci.h"
> +
> +STATIC
> +VOID
> +CdnsPciConfigRegion (
> + EFI_CPU_IO2_PROTOCOL *CpuIo,
> + IN UINT32 Region,
> + IN UINT32 Descriptor,
> + IN UINT32 TransAddr,
> + IN UINT32 TransAddrBits,
> + IN UINT32 BaseAddr,
> + IN UINT32 BaseAddrBits
> + )
> +{
> + UINTN RegionBaseAddr = PCIE_AXI + (Region * PCIE_AXI_REGION_OFF);
> +
> + PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_TRANS0_OFF,
> + TransAddr | TransAddrBits);
> + PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_DESC_OFF,
> + Descriptor);
> + PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_BASE0_OFF,
> + BaseAddr | BaseAddrBits);
> +}
> +
> +STATIC
> +VOID
> +CdnsPciRegInit(
> + EFI_CPU_IO2_PROTOCOL *CpuIo
> +)
> +{
> + UINT32 Value;
> +
> + // Setup the class code as PCIe Host Bridge.
> + PCIE_ROOTPORT_WRITE32 (PCIE_RP + PCIE_PCI_CLASSCODE, PCIE_BRIDGE_CLASSCODE);
> +
> + // Set up the BARs via the Root Port registers
> + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value);
> + PCIE_ROOTPORT_WRITE32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value | (1 << PCIE_RCBARPIE));
> +
> + // Allow incoming writes
> + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR0_IB, PCIE_AXI_BITS_32);
> + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR1_IB, PCIE_AXI_BITS_32);
> + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_NO_BAR_IB, PCIE_AXI_BITS_32);
> +
> + // Set up region 0 for Type 0 write (bus 0 and 1), size 2MB
> + CdnsPciConfigRegion (
> + CpuIo,
> + 0,
> + PCIE_AXI_DESC_TYPE0,
> + PCIE_ECAM_BASE,
> + PCIE_AXI_BITS_25,
> + 0,
> + PCIE_AXI_BITS_21
> + );
> +
> + // Set up region 1 for Type 1 writes (bus 2 upwards), size (32-2)MB
> + CdnsPciConfigRegion(
> + CpuIo,
> + 1,
> + PCIE_AXI_DESC_TYPE1,
> + PCIE_ECAM_BASE + (2*PCIE_BUS_SIZE),
> + PCIE_AXI_BITS_25,
> + 2*PCIE_BUS_SIZE,
> + PCIE_AXI_BITS_25
> + );
> +
> + // Set up region 2 for memory write, size 16MB
> + CdnsPciConfigRegion(
> + CpuIo,
> + 2,
> + PCIE_AXI_DESC_MEM,
> + PCIE_MEM32_BASE,
> + PCIE_AXI_BITS_25,
> + (PCIE_MEM32_BASE - PCIE_ECAM_BASE),
> + PCIE_AXI_BITS_24
> + );
> +
> + // Set up region 3 for IO write, size 16MB
> + CdnsPciConfigRegion(
> + CpuIo,
> + 3,
> + PCIE_AXI_DESC_IO,
> + PCIE_IO_BASE,
> + PCIE_AXI_BITS_25,
> + (PCIE_IO_BASE - PCIE_ECAM_BASE),
> + PCIE_AXI_BITS_24
> + );
Thanks - this is exactly what I was hoping for!
I'll leave for Ard to comment on hos bits, but:
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> +}
> +
> +EFI_STATUS
> +HWPciRbInit (
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + UINT32 Count;
> + EFI_CPU_IO2_PROTOCOL *CpuIo;
> + EFI_STATUS Status;
> + UINT32 Value;
> +
> + PCI_TRACE ("HWPciRbInit()");
> +
> + PCI_TRACE ("PCIe Setting up Address Translation");
> +
> + Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL,
> + (VOID **)&CpuIo);
> + ASSERT_EFI_ERROR (Status);
> +
> + // Check for link up
> + for (Count = 0; Count < PCIE_LINK_TIMEOUT_COUNT; Count++) {
> + gBS->Stall (PCIE_LINK_TIMEOUT_WAIT_US);
> + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_LINK_CTRL_STATUS, Value);
> + if (Value & PCIE_LINK_UP) {
> + break;
> + }
> + }
> + if (!(Value & PCIE_LINK_UP)) {
> + DEBUG ((DEBUG_ERROR, "PCIe link not up: %x.\n", Value));
> + return EFI_NOT_READY;
> + }
> +
> + // Initialise configuration registers
> + CdnsPciRegInit(CpuIo);
> +
> + return EFI_SUCCESS;
> +}
> diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
> new file mode 100644
> index 0000000..08faece
> --- /dev/null
> +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
> @@ -0,0 +1,88 @@
> +/** @file
> +* Header for Cadence PCIe Root Complex
> +*
> +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __CDNS_PCI_H__
> +#define __CDNS_PCI_H__
> +
> +#include <Protocol/CpuIo2.h>
> +
> +#define PCIE_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress)
> +#define PCIE_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize)
> +#define PCIE_IO_BASE (FixedPcdGet64(PcdPciIoTranslation) + FixedPcdGet64 (PcdPciIoBase))
> +#define PCIE_IO_SIZE FixedPcdGet64 (PcdPciIoSize)
> +#define PCIE_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base)
> +#define PCIE_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size)
> +
> +#define PCIE_BUS_SIZE SIZE_1MB
> +
> +#define PCIE_LINK_TIMEOUT_WAIT_US 1000 // microseconds
> +#define PCIE_LINK_TIMEOUT_COUNT 1000
> +
> +#define PCI_TRACE(txt) DEBUG((DEBUG_VERBOSE, "CDNS_PCI: " txt "\n"))
> +
> +#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); }
> +#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); }
> +#ifdef CDNS_B2B
> +#define PCIE1_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Value); }
> +#define PCIE1_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Val); }
> +#endif
> +
> +/*
> + * PCIe Core Configuration Register offsets
> + */
> +
> +// Root Port Configuration
> +#define PCIE_RP 0x00200000
> +#define PCIE_PCI_CLASSCODE 0x8
> +
> +// Local Management
> +#define PCIE_LM 0x00100000
> +#define PCIE_LINK_CTRL_STATUS 0x00
> +#define PCIE_RP_BAR_CONFIG 0x300
> +
> +// AXI Configuration
> +#define PCIE_AXI 0x00400000
> +
> +#define PCIE_AXI_REGION_OFF 0x020
> +#define PCIE_AXI_REGION_TRANS0_OFF 0x000
> +#define PCIE_AXI_REGION_DESC_OFF 0x008
> +#define PCIE_AXI_REGION_BASE0_OFF 0x018
> +
> +#define PCIE_AXI_BAR0_IB 0x800
> +#define PCIE_AXI_BAR1_IB 0x808
> +#define PCIE_AXI_NO_BAR_IB 0x810
> +
> +/*
> + * PCIe Core Configuration Register values
> + */
> +
> +#define PCIE_BRIDGE_CLASSCODE 0x06040000
> +#define PCIE_LINK_UP 0x01
> +#define PCIE_RCBARPIE 0x19
> +
> +// AXI Region Address Translation/Base Address bits values
> +#define PCIE_AXI_BITS_21 20
> +#define PCIE_AXI_BITS_24 23
> +#define PCIE_AXI_BITS_25 24
> +#define PCIE_AXI_BITS_32 31
> +
> +// AXI Region Outbound PCIe Descriptor Register values
> +#define PCIE_AXI_DESC_TYPE0 0x80000A
> +#define PCIE_AXI_DESC_TYPE1 0x80000B
> +#define PCIE_AXI_DESC_MEM 0x800002
> +#define PCIE_AXI_DESC_IO 0x800006
> +
> +#endif
> diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
> new file mode 100644
> index 0000000..f58cac3
> --- /dev/null
> +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
> @@ -0,0 +1,188 @@
> +/** @file
> + PCI Host Bridge support for the Cadence PCIe Root Complex
> +
> + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> + Copyright (c) 2017, Cadence Design Systems. All rights reserved.
> +
> + This program and the accompanying materials are licensed and made available
> + under the terms and conditions of the BSD License which accompanies this
> + distribution. The full text of the license may be found at
> + http://opensource.org/licenses/bsd-license.php.
> +
> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +
> +**/
> +#include <Library/DebugLib.h>
> +#include <Library/DevicePathLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/PciHostBridgeLib.h>
> +
> +#include <PiDxe.h>
> +
> +#include <Protocol/PciHostBridgeResourceAllocation.h>
> +#include <Protocol/PciRootBridgeIo.h>
> +
> +#pragma pack(1)
> +typedef struct {
> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
> +#pragma pack ()
> +
> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
> + {
> + {
> + ACPI_DEVICE_PATH,
> + ACPI_DP,
> + {
> + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
> + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
> + }
> + },
> + EISA_PNP_ID(0x0A03), // PCI
> + 0
> + }, {
> + END_DEVICE_PATH_TYPE,
> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
> + {
> + END_DEVICE_PATH_LENGTH,
> + 0
> + }
> + }
> +};
> +
> +STATIC PCI_ROOT_BRIDGE mRootBridge = {
> + 0, // Segment
> + 0, // Supports
> + 0, // Attributes
> + TRUE, // DmaAbove4G
> + FALSE, // NoExtendedConfigSpace
> + FALSE, // ResourceAssigned
> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM, // AllocationAttributes
> + {
> + // Bus
> + FixedPcdGet32 (PcdPciBusMin),
> + FixedPcdGet32 (PcdPciBusMax)
> + }, {
> + // Io
> + FixedPcdGet64 (PcdPciIoBase),
> + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
> + }, {
> + // Mem
> + FixedPcdGet32 (PcdPciMmio32Base),
> + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1
> + }, {
> + // MemAbove4G
> + MAX_UINT64,
> + 0
> + }, {
> + // PMem
> + MAX_UINT64,
> + 0
> + }, {
> + // PMemAbove4G
> + MAX_UINT64,
> + 0
> + },
> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath
> +};
> +
> +/**
> + Return all the root bridge instances in an array.
> +
> + @param Count Return the count of root bridge instances.
> +
> + @return All the root bridge instances in an array.
> + The array should be passed into PciHostBridgeFreeRootBridges()
> + when it's not used.
> +**/
> +PCI_ROOT_BRIDGE *
> +EFIAPI
> +PciHostBridgeGetRootBridges (
> + UINTN *Count
> + )
> +{
> + *Count = 1;
> +
> + return &mRootBridge;
> +}
> +
> +/**
> + Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
> +
> + @param Bridges The root bridge instances array.
> + @param Count The count of the array.
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeFreeRootBridges (
> + PCI_ROOT_BRIDGE *Bridges,
> + UINTN Count
> + )
> +{
> +}
> +
> +#ifndef MDEPKG_NDEBUG
> +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = {
> + L"Mem", L"I/O", L"Bus"
> +};
> +#endif
> +
> +/**
> + Inform the platform that the resource conflict happens.
> +
> + @param HostBridgeHandle Handle of the Host Bridge.
> + @param Configuration Pointer to PCI I/O and PCI memory resource
> + descriptors. The Configuration contains the resources
> + for all the root bridges. The resource for each root
> + bridge is terminated with END descriptor and an
> + additional END is appended indicating the end of the
> + entire resources. The resource descriptor field
> + values follow the description in
> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
> + .SubmitResources().
> +**/
> +VOID
> +EFIAPI
> +PciHostBridgeResourceConflict (
> + EFI_HANDLE HostBridgeHandle,
> + VOID *Configuration
> + )
> +{
> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
> + UINTN RootBridgeIndex;
> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
> +
> + RootBridgeIndex = 0;
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
> + ASSERT (Descriptor->ResType <
> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)
> + );
> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
> + Descriptor->AddrLen, Descriptor->AddrRangeMax
> + ));
> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
> + ((Descriptor->SpecificFlag &
> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
> + ) != 0) ? L" (Prefetchable)" : L""
> + ));
> + }
> + }
> + //
> + // Skip the END descriptor for root bridge
> + //
> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
> + );
> + }
> +}
> diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
> new file mode 100644
> index 0000000..b17a96c
> --- /dev/null
> +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
> @@ -0,0 +1,73 @@
> +## @file
> +# PCI Host Bridge Library instance for Cadence PCIe Root Complex
> +#
> +# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
> +# Copyright (c) 2017, Cadence Design Systems. All rights reserved.
> +#
> +# This program and the accompanying materials are licensed and made available
> +# under the terms and conditions of the BSD License which accompanies this
> +# distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
> +# IMPLIED.
> +#
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 1.25
> + BASE_NAME = CdnsPciHostBridgeLib
> + FILE_GUID = d92c722c-87f9-4988-843e-dffd6bc8c5e3
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
> + CONSTRUCTOR = HWPciRbInit
> +
> +#
> +# The following information is for reference only and not required by the build
> +# tools.
> +#
> +# VALID_ARCHITECTURES = AARCH64 ARM
> +#
> +
> +[Sources]
> + CdnsPciHostBridgeLib.c
> + CdnsPci.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + CadencePkg/CadenceCspPkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + MdePkg/MdePkg.dec
> +
> +[LibraryClasses]
> + BaseLib
> + DebugLib
> + DevicePathLib
> + IoLib
> + MemoryAllocationLib
> + UefiBootServicesTableLib
> +
> +[Pcd]
> + gArmTokenSpaceGuid.PcdSystemMemoryBase
> + gArmTokenSpaceGuid.PcdSystemMemorySize
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdPciBusMin
> + gArmTokenSpaceGuid.PcdPciBusMax
> + gArmTokenSpaceGuid.PcdPciIoBase
> + gArmTokenSpaceGuid.PcdPciIoSize
> + gArmTokenSpaceGuid.PcdPciIoTranslation
> + gArmTokenSpaceGuid.PcdPciMmio32Base
> + gArmTokenSpaceGuid.PcdPciMmio32Size
> + gArmTokenSpaceGuid.PcdPciMmio32Translation
> + gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress
> + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
> + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize
> +
> +[Protocols]
> + gEfiCpuIo2ProtocolGuid ## CONSUMES
> +
> +[Depex]
> + gEfiCpuIo2ProtocolGuid
> --
> 2.2.2
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [staging/cadence-aarch64 PATCH v3 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex.
2017-06-22 15:12 ` Leif Lindholm
@ 2017-06-23 18:43 ` Ard Biesheuvel
0 siblings, 0 replies; 16+ messages in thread
From: Ard Biesheuvel @ 2017-06-23 18:43 UTC (permalink / raw)
To: Leif Lindholm
Cc: Scott Telford, edk2-devel@lists.01.org, Graeme Gregory,
afish@apple.com, Kinney, Michael D
On 22 June 2017 at 15:12, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Thu, Jun 22, 2017 at 10:31:58AM +0100, Scott Telford wrote:
>> Add PciHostBridgeLib implementation for the Cadence PCIe Root Complex.
>> This library is derived from
>> Platforms/ARM/Juno/Library/JunoPciHostBridgeLib in OpenPlatformPkg.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Scott Telford <stelford@cadence.com>
>> ---
>> .../Library/CadencePciHostBridgeLib/CdnsPci.c | 149 ++++++++++++++++
>> .../Library/CadencePciHostBridgeLib/CdnsPci.h | 88 ++++++++++
>> .../CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c | 188 +++++++++++++++++++++
>> .../CdnsPciHostBridgeLib.inf | 73 ++++++++
>> 4 files changed, 498 insertions(+)
>> create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
>> create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
>> create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
>> create mode 100644 CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
>>
>> diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
>> new file mode 100644
>> index 0000000..3114843
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.c
>> @@ -0,0 +1,149 @@
>> +/** @file
>> +* Initialize the Cadence PCIe Root complex
>> +*
>> +* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#include <Library/BaseLib.h>
>> +#include <Library/CspSysReg.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/UefiBootServicesTableLib.h>
>> +
>> +#include <Protocol/Cpu.h>
>> +
>> +#include "CdnsPci.h"
>> +
>> +STATIC
>> +VOID
>> +CdnsPciConfigRegion (
>> + EFI_CPU_IO2_PROTOCOL *CpuIo,
>> + IN UINT32 Region,
>> + IN UINT32 Descriptor,
>> + IN UINT32 TransAddr,
>> + IN UINT32 TransAddrBits,
>> + IN UINT32 BaseAddr,
>> + IN UINT32 BaseAddrBits
>> + )
>> +{
>> + UINTN RegionBaseAddr = PCIE_AXI + (Region * PCIE_AXI_REGION_OFF);
>> +
>> + PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_TRANS0_OFF,
>> + TransAddr | TransAddrBits);
>> + PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_DESC_OFF,
>> + Descriptor);
>> + PCIE_ROOTPORT_WRITE32 (RegionBaseAddr + PCIE_AXI_REGION_BASE0_OFF,
>> + BaseAddr | BaseAddrBits);
>> +}
>> +
>> +STATIC
>> +VOID
>> +CdnsPciRegInit(
>> + EFI_CPU_IO2_PROTOCOL *CpuIo
>> +)
>> +{
>> + UINT32 Value;
>> +
>> + // Setup the class code as PCIe Host Bridge.
>> + PCIE_ROOTPORT_WRITE32 (PCIE_RP + PCIE_PCI_CLASSCODE, PCIE_BRIDGE_CLASSCODE);
>> +
>> + // Set up the BARs via the Root Port registers
>> + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value);
>> + PCIE_ROOTPORT_WRITE32 (PCIE_LM + PCIE_RP_BAR_CONFIG, Value | (1 << PCIE_RCBARPIE));
>> +
>> + // Allow incoming writes
>> + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR0_IB, PCIE_AXI_BITS_32);
>> + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_BAR1_IB, PCIE_AXI_BITS_32);
>> + PCIE_ROOTPORT_WRITE32 (PCIE_AXI + PCIE_AXI_NO_BAR_IB, PCIE_AXI_BITS_32);
>> +
>> + // Set up region 0 for Type 0 write (bus 0 and 1), size 2MB
>> + CdnsPciConfigRegion (
>> + CpuIo,
>> + 0,
>> + PCIE_AXI_DESC_TYPE0,
>> + PCIE_ECAM_BASE,
>> + PCIE_AXI_BITS_25,
>> + 0,
>> + PCIE_AXI_BITS_21
>> + );
>> +
>> + // Set up region 1 for Type 1 writes (bus 2 upwards), size (32-2)MB
>> + CdnsPciConfigRegion(
>> + CpuIo,
>> + 1,
>> + PCIE_AXI_DESC_TYPE1,
>> + PCIE_ECAM_BASE + (2*PCIE_BUS_SIZE),
>> + PCIE_AXI_BITS_25,
>> + 2*PCIE_BUS_SIZE,
>> + PCIE_AXI_BITS_25
>> + );
>> +
It is still not fully clear to me how this works, i.e., how type0
cycles for bus 1 get routed correctly. But if it works, I'm fine with
it. (Obviously, you know the IP best)
>> + // Set up region 2 for memory write, size 16MB
>> + CdnsPciConfigRegion(
>> + CpuIo,
>> + 2,
>> + PCIE_AXI_DESC_MEM,
>> + PCIE_MEM32_BASE,
>> + PCIE_AXI_BITS_25,
>> + (PCIE_MEM32_BASE - PCIE_ECAM_BASE),
>> + PCIE_AXI_BITS_24
>> + );
>> +
>> + // Set up region 3 for IO write, size 16MB
>> + CdnsPciConfigRegion(
>> + CpuIo,
>> + 3,
>> + PCIE_AXI_DESC_IO,
>> + PCIE_IO_BASE,
>> + PCIE_AXI_BITS_25,
>> + (PCIE_IO_BASE - PCIE_ECAM_BASE),
>> + PCIE_AXI_BITS_24
>> + );
>
> Thanks - this is exactly what I was hoping for!
> I'll leave for Ard to comment on hos bits, but:
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> +}
>> +
>> +EFI_STATUS
>> +HWPciRbInit (
>> + IN EFI_HANDLE ImageHandle,
>> + IN EFI_SYSTEM_TABLE *SystemTable
>> + )
>> +{
>> + UINT32 Count;
>> + EFI_CPU_IO2_PROTOCOL *CpuIo;
>> + EFI_STATUS Status;
>> + UINT32 Value;
>> +
>> + PCI_TRACE ("HWPciRbInit()");
>> +
>> + PCI_TRACE ("PCIe Setting up Address Translation");
>> +
>> + Status = gBS->LocateProtocol (&gEfiCpuIo2ProtocolGuid, NULL,
>> + (VOID **)&CpuIo);
>> + ASSERT_EFI_ERROR (Status);
>> +
>> + // Check for link up
>> + for (Count = 0; Count < PCIE_LINK_TIMEOUT_COUNT; Count++) {
>> + gBS->Stall (PCIE_LINK_TIMEOUT_WAIT_US);
>> + PCIE_ROOTPORT_READ32 (PCIE_LM + PCIE_LINK_CTRL_STATUS, Value);
>> + if (Value & PCIE_LINK_UP) {
>> + break;
>> + }
>> + }
>> + if (!(Value & PCIE_LINK_UP)) {
>> + DEBUG ((DEBUG_ERROR, "PCIe link not up: %x.\n", Value));
>> + return EFI_NOT_READY;
>> + }
>> +
>> + // Initialise configuration registers
>> + CdnsPciRegInit(CpuIo);
>> +
>> + return EFI_SUCCESS;
>> +}
>> diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
>> new file mode 100644
>> index 0000000..08faece
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPci.h
>> @@ -0,0 +1,88 @@
>> +/** @file
>> +* Header for Cadence PCIe Root Complex
>> +*
>> +* Copyright (c) 2011-2015, ARM Ltd. All rights reserved.
>> +* Copyright (c) 2017, Cadence Design Systems. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#ifndef __CDNS_PCI_H__
>> +#define __CDNS_PCI_H__
>> +
>> +#include <Protocol/CpuIo2.h>
>> +
>> +#define PCIE_ECAM_BASE FixedPcdGet64 (PcdPciConfigurationSpaceBaseAddress)
>> +#define PCIE_ECAM_SIZE FixedPcdGet64 (PcdPciConfigurationSpaceSize)
>> +#define PCIE_IO_BASE (FixedPcdGet64(PcdPciIoTranslation) + FixedPcdGet64 (PcdPciIoBase))
>> +#define PCIE_IO_SIZE FixedPcdGet64 (PcdPciIoSize)
>> +#define PCIE_MEM32_BASE FixedPcdGet64 (PcdPciMmio32Base)
>> +#define PCIE_MEM32_SIZE FixedPcdGet64 (PcdPciMmio32Size)
>> +
>> +#define PCIE_BUS_SIZE SIZE_1MB
>> +
>> +#define PCIE_LINK_TIMEOUT_WAIT_US 1000 // microseconds
>> +#define PCIE_LINK_TIMEOUT_COUNT 1000
>> +
>> +#define PCI_TRACE(txt) DEBUG((DEBUG_VERBOSE, "CDNS_PCI: " txt "\n"))
>> +
>> +#define PCIE_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Value); }
>> +#define PCIE_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcieRootPortBaseAddress)+(Add)),1,&Val); }
>> +#ifdef CDNS_B2B
>> +#define PCIE1_ROOTPORT_WRITE32(Add, Val) { UINT32 Value = (UINT32)(Val); CpuIo->Mem.Write (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Value); }
>> +#define PCIE1_ROOTPORT_READ32(Add, Val) { CpuIo->Mem.Read (CpuIo,EfiCpuIoWidthUint32,(UINT64)(PcdGet64 (PcdPcie1RootPortBaseAddress)+(Add)),1,&Val); }
>> +#endif
>> +
>> +/*
>> + * PCIe Core Configuration Register offsets
>> + */
>> +
>> +// Root Port Configuration
>> +#define PCIE_RP 0x00200000
>> +#define PCIE_PCI_CLASSCODE 0x8
>> +
>> +// Local Management
>> +#define PCIE_LM 0x00100000
>> +#define PCIE_LINK_CTRL_STATUS 0x00
>> +#define PCIE_RP_BAR_CONFIG 0x300
>> +
>> +// AXI Configuration
>> +#define PCIE_AXI 0x00400000
>> +
>> +#define PCIE_AXI_REGION_OFF 0x020
>> +#define PCIE_AXI_REGION_TRANS0_OFF 0x000
>> +#define PCIE_AXI_REGION_DESC_OFF 0x008
>> +#define PCIE_AXI_REGION_BASE0_OFF 0x018
>> +
>> +#define PCIE_AXI_BAR0_IB 0x800
>> +#define PCIE_AXI_BAR1_IB 0x808
>> +#define PCIE_AXI_NO_BAR_IB 0x810
>> +
>> +/*
>> + * PCIe Core Configuration Register values
>> + */
>> +
>> +#define PCIE_BRIDGE_CLASSCODE 0x06040000
>> +#define PCIE_LINK_UP 0x01
>> +#define PCIE_RCBARPIE 0x19
>> +
>> +// AXI Region Address Translation/Base Address bits values
>> +#define PCIE_AXI_BITS_21 20
>> +#define PCIE_AXI_BITS_24 23
>> +#define PCIE_AXI_BITS_25 24
>> +#define PCIE_AXI_BITS_32 31
>> +
>> +// AXI Region Outbound PCIe Descriptor Register values
>> +#define PCIE_AXI_DESC_TYPE0 0x80000A
>> +#define PCIE_AXI_DESC_TYPE1 0x80000B
>> +#define PCIE_AXI_DESC_MEM 0x800002
>> +#define PCIE_AXI_DESC_IO 0x800006
>> +
>> +#endif
>> diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
>> new file mode 100644
>> index 0000000..f58cac3
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.c
>> @@ -0,0 +1,188 @@
>> +/** @file
>> + PCI Host Bridge support for the Cadence PCIe Root Complex
>> +
>> + Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
>> + Copyright (c) 2017, Cadence Design Systems. All rights reserved.
>> +
>> + This program and the accompanying materials are licensed and made available
>> + under the terms and conditions of the BSD License which accompanies this
>> + distribution. The full text of the license may be found at
>> + http://opensource.org/licenses/bsd-license.php.
>> +
>> + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT
>> + WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +
>> +**/
>> +#include <Library/DebugLib.h>
>> +#include <Library/DevicePathLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/MemoryAllocationLib.h>
>> +#include <Library/PcdLib.h>
>> +#include <Library/PciHostBridgeLib.h>
>> +
>> +#include <PiDxe.h>
>> +
>> +#include <Protocol/PciHostBridgeResourceAllocation.h>
>> +#include <Protocol/PciRootBridgeIo.h>
>> +
>> +#pragma pack(1)
>> +typedef struct {
>> + ACPI_HID_DEVICE_PATH AcpiDevicePath;
>> + EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
>> +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
>> +#pragma pack ()
>> +
>> +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
>> + {
>> + {
>> + ACPI_DEVICE_PATH,
>> + ACPI_DP,
>> + {
>> + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)),
>> + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8)
>> + }
>> + },
>> + EISA_PNP_ID(0x0A03), // PCI
>> + 0
>> + }, {
>> + END_DEVICE_PATH_TYPE,
>> + END_ENTIRE_DEVICE_PATH_SUBTYPE,
>> + {
>> + END_DEVICE_PATH_LENGTH,
>> + 0
>> + }
>> + }
>> +};
>> +
>> +STATIC PCI_ROOT_BRIDGE mRootBridge = {
>> + 0, // Segment
>> + 0, // Supports
>> + 0, // Attributes
>> + TRUE, // DmaAbove4G
>> + FALSE, // NoExtendedConfigSpace
>> + FALSE, // ResourceAssigned
>> + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM, // AllocationAttributes
>> + {
>> + // Bus
>> + FixedPcdGet32 (PcdPciBusMin),
>> + FixedPcdGet32 (PcdPciBusMax)
>> + }, {
>> + // Io
>> + FixedPcdGet64 (PcdPciIoBase),
>> + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
>> + }, {
>> + // Mem
>> + FixedPcdGet32 (PcdPciMmio32Base),
>> + FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1
>> + }, {
>> + // MemAbove4G
>> + MAX_UINT64,
>> + 0
>> + }, {
>> + // PMem
>> + MAX_UINT64,
>> + 0
>> + }, {
>> + // PMemAbove4G
>> + MAX_UINT64,
>> + 0
>> + },
>> + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath
>> +};
>> +
>> +/**
>> + Return all the root bridge instances in an array.
>> +
>> + @param Count Return the count of root bridge instances.
>> +
>> + @return All the root bridge instances in an array.
>> + The array should be passed into PciHostBridgeFreeRootBridges()
>> + when it's not used.
>> +**/
>> +PCI_ROOT_BRIDGE *
>> +EFIAPI
>> +PciHostBridgeGetRootBridges (
>> + UINTN *Count
>> + )
>> +{
>> + *Count = 1;
>> +
>> + return &mRootBridge;
>> +}
>> +
>> +/**
>> + Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
>> +
>> + @param Bridges The root bridge instances array.
>> + @param Count The count of the array.
>> +**/
>> +VOID
>> +EFIAPI
>> +PciHostBridgeFreeRootBridges (
>> + PCI_ROOT_BRIDGE *Bridges,
>> + UINTN Count
>> + )
>> +{
>> +}
>> +
>> +#ifndef MDEPKG_NDEBUG
>> +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = {
>> + L"Mem", L"I/O", L"Bus"
>> +};
>> +#endif
>> +
>> +/**
>> + Inform the platform that the resource conflict happens.
>> +
>> + @param HostBridgeHandle Handle of the Host Bridge.
>> + @param Configuration Pointer to PCI I/O and PCI memory resource
>> + descriptors. The Configuration contains the resources
>> + for all the root bridges. The resource for each root
>> + bridge is terminated with END descriptor and an
>> + additional END is appended indicating the end of the
>> + entire resources. The resource descriptor field
>> + values follow the description in
>> + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
>> + .SubmitResources().
>> +**/
>> +VOID
>> +EFIAPI
>> +PciHostBridgeResourceConflict (
>> + EFI_HANDLE HostBridgeHandle,
>> + VOID *Configuration
>> + )
>> +{
>> + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
>> + UINTN RootBridgeIndex;
>> + DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
>> +
>> + RootBridgeIndex = 0;
>> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
>> + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
>> + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
>> + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
>> + ASSERT (Descriptor->ResType <
>> + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)
>> + );
>> + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
>> + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
>> + Descriptor->AddrLen, Descriptor->AddrRangeMax
>> + ));
>> + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
>> + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n",
>> + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
>> + ((Descriptor->SpecificFlag &
>> + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
>> + ) != 0) ? L" (Prefetchable)" : L""
>> + ));
>> + }
>> + }
>> + //
>> + // Skip the END descriptor for root bridge
>> + //
>> + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
>> + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
>> + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
>> + );
>> + }
>> +}
>> diff --git a/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
>> new file mode 100644
>> index 0000000..b17a96c
>> --- /dev/null
>> +++ b/CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
>> @@ -0,0 +1,73 @@
>> +## @file
>> +# PCI Host Bridge Library instance for Cadence PCIe Root Complex
>> +#
>> +# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>
>> +# Copyright (c) 2017, Cadence Design Systems. All rights reserved.
>> +#
>> +# This program and the accompanying materials are licensed and made available
>> +# under the terms and conditions of the BSD License which accompanies this
>> +# distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR
>> +# IMPLIED.
>> +#
>> +#
>> +##
>> +
>> +[Defines]
>> + INF_VERSION = 1.25
>> + BASE_NAME = CdnsPciHostBridgeLib
>> + FILE_GUID = d92c722c-87f9-4988-843e-dffd6bc8c5e3
>> + MODULE_TYPE = DXE_DRIVER
>> + VERSION_STRING = 1.0
>> + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER
>> + CONSTRUCTOR = HWPciRbInit
>> +
>> +#
>> +# The following information is for reference only and not required by the build
>> +# tools.
>> +#
>> +# VALID_ARCHITECTURES = AARCH64 ARM
>> +#
>> +
>> +[Sources]
>> + CdnsPciHostBridgeLib.c
>> + CdnsPci.c
>> +
>> +[Packages]
>> + ArmPkg/ArmPkg.dec
>> + CadencePkg/CadenceCspPkg.dec
>> + MdeModulePkg/MdeModulePkg.dec
>> + MdePkg/MdePkg.dec
>> +
>> +[LibraryClasses]
>> + BaseLib
>> + DebugLib
>> + DevicePathLib
>> + IoLib
>> + MemoryAllocationLib
>> + UefiBootServicesTableLib
>> +
>> +[Pcd]
>> + gArmTokenSpaceGuid.PcdSystemMemoryBase
>> + gArmTokenSpaceGuid.PcdSystemMemorySize
>> +
>> +[FixedPcd]
>> + gArmTokenSpaceGuid.PcdPciBusMin
>> + gArmTokenSpaceGuid.PcdPciBusMax
>> + gArmTokenSpaceGuid.PcdPciIoBase
>> + gArmTokenSpaceGuid.PcdPciIoSize
>> + gArmTokenSpaceGuid.PcdPciIoTranslation
>> + gArmTokenSpaceGuid.PcdPciMmio32Base
>> + gArmTokenSpaceGuid.PcdPciMmio32Size
>> + gArmTokenSpaceGuid.PcdPciMmio32Translation
>> + gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress
>> + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress
>> + gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize
>> +
>> +[Protocols]
>> + gEfiCpuIo2ProtocolGuid ## CONSUMES
>> +
>> +[Depex]
>> + gEfiCpuIo2ProtocolGuid
>> --
>> 2.2.2
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [staging/cadence-aarch64 PATCH v3 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform.
2017-06-22 9:31 [staging/cadence-aarch64 PATCH v3 0/6] CadencePkg: Add package for Cadence hardware IP support Scott Telford
` (2 preceding siblings ...)
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 3/6] CadencePkg: Add PCI host bridge library for Cadence PCIe Root Complex Scott Telford
@ 2017-06-22 9:31 ` Scott Telford
2017-06-22 15:21 ` Leif Lindholm
2017-06-22 9:32 ` [staging/cadence-aarch64 PATCH v3 5/6] CadencePkg: Add ACPI tables " Scott Telford
2017-06-22 9:32 ` [staging/cadence-aarch64 PATCH v3 6/6] CadencePkg: Add .dsc, .fdf and .dec files " Scott Telford
5 siblings, 1 reply; 16+ messages in thread
From: Scott Telford @ 2017-06-22 9:31 UTC (permalink / raw)
To: edk2-devel, leif.lindholm, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
Add SEC phase implementation for Cadence CSP platform configured with
a single Cortex-A53 processor and GIC-500.
Based on ArmPlatformPkg/Sec, with required parts of
ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib integrated (both now deleted
from edk2 master).
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford <stelford@cadence.com>
---
CadencePkg/Sec/AArch64/Arch.c | 25 +++
CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S | 27 +++
CadencePkg/Sec/AArch64/Helper.S | 93 ++++++++
CadencePkg/Sec/AArch64/SecEntryPoint.S | 139 ++++++++++++
CadencePkg/Sec/Sec.c | 335 ++++++++++++++++++++++++++++
CadencePkg/Sec/Sec.inf | 85 +++++++
CadencePkg/Sec/SecInternal.h | 105 +++++++++
7 files changed, 809 insertions(+)
create mode 100644 CadencePkg/Sec/AArch64/Arch.c
create mode 100644 CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
create mode 100644 CadencePkg/Sec/AArch64/Helper.S
create mode 100644 CadencePkg/Sec/AArch64/SecEntryPoint.S
create mode 100644 CadencePkg/Sec/Sec.c
create mode 100644 CadencePkg/Sec/Sec.inf
create mode 100644 CadencePkg/Sec/SecInternal.h
diff --git a/CadencePkg/Sec/AArch64/Arch.c b/CadencePkg/Sec/AArch64/Arch.c
new file mode 100644
index 0000000..6e7d58e
--- /dev/null
+++ b/CadencePkg/Sec/AArch64/Arch.c
@@ -0,0 +1,25 @@
+/** @file
+*
+* Copyright (c) 2013, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Chipset/AArch64.h>
+
+VOID
+EFIAPI
+ArmSecArchTrustzoneInit (
+ VOID
+ )
+{
+ // Do not trap any access to Floating Point and Advanced SIMD in EL3.
+ ArmWriteCptr (0);
+}
diff --git a/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
new file mode 100644
index 0000000..531de63
--- /dev/null
+++ b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
@@ -0,0 +1,27 @@
+#------------------------------------------------------------------------------
+#
+# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD Licese
+# which accompanies this distribution. The full text of the license may be foun at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+#include <AsmMacroIoLibV8.h>
+
+ASM_FUNC(ArmReadCpuExCr)
+ mrs x0, S3_1_c15_c2_1
+ ret
+
+ASM_FUNC(ArmWriteCpuExCr)
+ msr S3_1_c15_c2_1, x0
+ dsb sy
+ isb
+ ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/CadencePkg/Sec/AArch64/Helper.S b/CadencePkg/Sec/AArch64/Helper.S
new file mode 100644
index 0000000..3b58e12
--- /dev/null
+++ b/CadencePkg/Sec/AArch64/Helper.S
@@ -0,0 +1,93 @@
+#========================================================================================
+# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http:#opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#=======================================================================================
+
+#include <AsmMacroIoLibV8.h>
+#include <Chipset/AArch64.h>
+
+#start of the code section
+.text
+.align 3
+
+GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)
+GCC_ASM_EXPORT(enter_monitor_mode)
+GCC_ASM_EXPORT(return_from_exception)
+GCC_ASM_EXPORT(copy_cpsr_into_spsr)
+GCC_ASM_EXPORT(set_non_secure_mode)
+
+// Switch from EL3 to NS-EL1
+ASM_PFX(SwitchToNSExceptionLevel1):
+ // Now setup our EL1. Controlled by EL2 config on Model
+ mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
+ orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
+
+ // Send all interrupts to their respective Exception levels for EL2
+ and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort
+ msr hcr_el2, x0 // Write back our settings
+
+ msr cptr_el2, xzr // Disable copro traps to EL2
+
+ msr sctlr_el2, xzr
+
+ // Enable architected timer access
+ mrs x0, cnthctl_el2
+ orr x0, x0, #3 // Enable EL1 access to timers
+ msr cnthctl_el2, x0
+
+ mrs x0, cntkctl_el1
+ orr x0, x0, #3 // EL0 access to counters
+ msr cntkctl_el1, x0
+
+ // Set ID regs
+ mrs x0, midr_el1
+ mrs x1, mpidr_el1
+ msr vpidr_el2, x0
+ msr vmpidr_el2, x1
+
+ ret
+
+
+// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7
+// we don't need a mode switch, just setup the Arguments and jump.
+// x0: Monitor World EntryPoint
+// x1: MpId
+// x2: SecBootMode
+// x3: Secure Monitor mode stack
+ASM_PFX(enter_monitor_mode):
+ mov x4, x0 // Swap EntryPoint and MpId registers
+ mov x0, x1
+ mov x1, x2
+ mov x2, x3
+ br x4
+
+// Put the address in correct ELR_ELx and do a eret.
+// We may need to do some config before we change to another Mode.
+ASM_PFX(return_from_exception):
+ msr elr_el3, x0
+ eret
+
+// For AArch64 we need to construct the spsr we want from individual bits and pieces.
+ASM_PFX(copy_cpsr_into_spsr):
+ mrs x0, CurrentEl // Get the current exception level we are running at.
+ mrs x1, SPSel // Which Stack are we using
+ orr x0, x0, x1
+ mrs x1, daif // Which interrupts are enabled
+ orr x0, x0, x1
+ msr spsr_el3, x0 // Write to spsr
+ ret
+
+// Get this from platform file.
+ASM_PFX(set_non_secure_mode):
+ msr spsr_el3, x0
+ ret
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/CadencePkg/Sec/AArch64/SecEntryPoint.S b/CadencePkg/Sec/AArch64/SecEntryPoint.S
new file mode 100644
index 0000000..06bea3c
--- /dev/null
+++ b/CadencePkg/Sec/AArch64/SecEntryPoint.S
@@ -0,0 +1,139 @@
+//
+// Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution. The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//
+
+#include <AutoGen.h>
+#include <AsmMacroIoLibV8.h>
+#include "SecInternal.h"
+
+.text
+.align 3
+
+GCC_ASM_IMPORT(CEntryPoint)
+GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)
+GCC_ASM_IMPORT(ArmPlatformGetCorePosition)
+GCC_ASM_IMPORT(ArmPlatformSecBootAction)
+GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
+GCC_ASM_IMPORT(ArmDisableInterrupts)
+GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
+GCC_ASM_IMPORT(ArmReadMpidr)
+GCC_ASM_IMPORT(ArmCallWFE)
+GCC_ASM_EXPORT(_ModuleEntryPoint)
+
+StartupAddr: .8byte ASM_PFX(CEntryPoint)
+
+ASM_PFX(_ModuleEntryPoint):
+
+// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
+// and configure the system accordingly. EL2 is default if possible.
+// If we started in EL3 we need to switch and run at EL2.
+// If we are running at EL2 stay in EL2
+// If we are starting at EL1 stay in EL1.
+
+// Sec only runs in EL3. Othewise we jump to PEI without changing anything.
+// If Sec runs we change to EL2 before switching to PEI.
+
+// Which EL are we running at? Every EL needs some level of setup...
+ EL1_OR_EL2_OR_EL3(x0)
+1:// If we are at EL1 or EL2 leave SEC for PEI.
+2:b ASM_PFX(JumpToPEI)
+ // If we are at EL3 we need to configure it and switch to EL2
+3:b ASM_PFX(MainEntryPoint)
+
+ASM_PFX(MainEntryPoint):
+ // First ensure all interrupts are disabled
+ bl ASM_PFX(ArmDisableInterrupts)
+
+ // Ensure that the MMU and caches are off
+ bl ASM_PFX(ArmDisableCachesAndMmu)
+
+ // By default, we are doing a cold boot
+ mov x10, #ARM_SEC_COLD_BOOT
+
+ // Jump to Platform Specific Boot Action function
+ bl ASM_PFX(ArmPlatformSecBootAction)
+
+_IdentifyCpu:
+ // Identify CPU ID
+ bl ASM_PFX(ArmReadMpidr)
+ // Keep a copy of the MpId register value
+ mov x5, x0
+
+ // Is it the Primary Core ?
+ bl ASM_PFX(ArmPlatformIsPrimaryCore)
+ cmp x0, #1
+ // Only the primary core initialize the memory (SMC)
+ b.eq _InitMem
+
+_WaitInitMem:
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
+ // Otherwise we have to wait the Primary Core to finish the initialization
+ cmp x10, #ARM_SEC_COLD_BOOT
+ b.ne _SetupSecondaryCoreStack
+
+ // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
+ bl ASM_PFX(ArmCallWFE)
+ // Now the Init Mem is initialized, we setup the secondary core stacks
+ b _SetupSecondaryCoreStack
+
+_InitMem:
+ // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
+ cmp x10, #ARM_SEC_COLD_BOOT
+ b.ne _SetupPrimaryCoreStack
+
+ // Initialize Init Boot Memory
+ bl ASM_PFX(ArmPlatformSecBootMemoryInit)
+
+_SetupPrimaryCoreStack:
+ // Get the top of the primary stacks (and the base of the secondary stacks)
+ MOV32 (x1, FixedPcdGet32(PcdCPUCoresSecStackBase))
+ MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize))
+ add x1, x1, x2
+
+ mov sp, x1
+ b _PrepareArguments
+
+_SetupSecondaryCoreStack:
+ // Get the top of the primary stacks (and the base of the secondary stacks)
+ MOV32 (x1, FixedPcdGet32(PcdCPUCoresSecStackBase))
+ MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize))
+ add x6, x1, x2
+
+ // Get the Core Position
+ mov x0, x5
+ bl ASM_PFX(ArmPlatformGetCorePosition)
+ // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
+ add x0, x0, #1
+
+ // StackOffset = CorePos * StackSize
+ MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize))
+ mul x0, x0, x2
+ // SP = StackBase + StackOffset
+ add sp, x6, x0
+
+_PrepareArguments:
+ // Move sec startup address into a data register
+ // Ensure we're jumping to FV version of the code (not boot remapped alias)
+ ldr x3, StartupAddr
+
+ // Jump to SEC C code
+ // r0 = mp_id
+ // r1 = Boot Mode
+ mov x0, x5
+ mov x1, x10
+ blr x3
+
+ ret
+
+ASM_PFX(JumpToPEI):
+ MOV32 (x0, FixedPcdGet32(PcdFvBaseAddress))
+ blr x0
diff --git a/CadencePkg/Sec/Sec.c b/CadencePkg/Sec/Sec.c
new file mode 100644
index 0000000..5b0244e
--- /dev/null
+++ b/CadencePkg/Sec/Sec.c
@@ -0,0 +1,335 @@
+/** @file
+* Main file supporting the SEC Phase on ARM Platforms
+*
+* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Chipset/ArmCortexA5x.h>
+#include <Library/ArmTrustedMonitorLib.h>
+#include <Library/ArmGenericTimerCounterLib.h>
+#include <Library/DebugAgentLib.h>
+#include <Library/IoLib.h>
+#include <Library/PrintLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/ArmGicLib.h>
+#include <Library/ArmPlatformLib.h>
+
+#include "SecInternal.h"
+
+#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
+
+#define ARM_GICR_WAKER 0x0014 // GIC Redistributor Wake Register
+#define ARM_GICR_IGROUPR0 0x0080 // GIC Redistributor Int Group Reg 0
+#define ARM_GICR_IGRPMODR0 0x0d00 // GIC Redistributor Int Group Mod Reg 0
+#define ARM_GICR_ICFGR1 0x0c04 // GIC Redistributor Int Config Reg 0
+
+
+VOID
+CEntryPoint (
+ IN UINTN MpId,
+ IN UINTN SecBootMode
+ )
+{
+ CHAR8 Buffer[100];
+ UINTN CharCount;
+ UINTN JumpAddress;
+
+ // Invalidate the data cache. Doesn't have to do the Data cache clean.
+ ArmInvalidateDataCache ();
+
+ // Invalidate Instruction Cache
+ ArmInvalidateInstructionCache ();
+
+ // Invalidate I & D TLBs
+ ArmInvalidateTlb ();
+
+ // CPU specific settings
+ ArmCpuSetup (MpId);
+
+ // Enable Floating Point Coprocessor if supported by the platform
+ if (FixedPcdGet32 (PcdVFPEnabled)) {
+ ArmEnableVFP ();
+ }
+
+ // Initialize peripherals that must be done at the early stage
+ // Example: Some L2 controller, interconnect, clock, DMC, etc
+ ArmPlatformSecInitialize (MpId);
+
+ // Primary CPU clears out the SCU tag RAMs, secondaries wait
+ if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {
+ if (ArmIsMpCore()) {
+ // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
+ ArmCallSEV ();
+ }
+
+ // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
+ // In non SEC modules the init call is in autogenerated code.
+ SerialPortInitialize ();
+
+ // Start talking
+ if (FixedPcdGetBool (PcdTrustzoneSupport)) {
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",
+ (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
+ } else {
+ CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",
+ (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
+ }
+ SerialPortWrite ((UINT8 *) Buffer, CharCount);
+
+ // Initialize the Debug Agent for Source Level Debugging
+ InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
+ SaveAndSetDebugTimerInterrupt (TRUE);
+
+ // Enable the GIC distributor and CPU Interface
+ // - no other Interrupts are enabled, doesn't have to worry about the priority.
+ // - all the cores are in secure state, use secure SGI's
+ ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));
+ ArmGicEnableInterruptInterface (PcdGet64(PcdGicInterruptInterfaceBase));
+ } else {
+ // Enable the GIC CPU Interface
+ ArmGicEnableInterruptInterface (PcdGet64(PcdGicInterruptInterfaceBase));
+ }
+
+ // Enable Full Access to CoProcessors
+ ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
+
+ // Test if Trustzone is supported on this platform
+ if (FixedPcdGetBool (PcdTrustzoneSupport)) {
+ if (ArmIsMpCore ()) {
+ // Setup SMP in Non Secure world
+ ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
+ }
+
+ // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
+ // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
+ ASSERT (((PcdGet64(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
+ ((PcdGet64(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
+
+ // Enter Monitor Mode
+ enter_monitor_mode (
+ (UINTN)TrustedWorldInitialization, MpId, SecBootMode,
+ (VOID*) (PcdGet64 (PcdCPUCoresSecMonStackBase) +
+ (PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosition (MpId) + 1)))
+ );
+ } else {
+ if (ArmPlatformIsPrimaryCore (MpId)) {
+ SerialPrint ("Trust Zone Configuration is disabled\n\r");
+ }
+
+ // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
+ // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
+ // Status Register as the the current one (CPSR).
+ copy_cpsr_into_spsr ();
+
+ // Call the Platform specific function to execute additional actions if required
+ JumpAddress = PcdGet64 (PcdFvBaseAddress);
+
+ ArmPlatformSecExtraAction (MpId, &JumpAddress);
+
+ NonTrustedWorldTransition (MpId, JumpAddress);
+ }
+ ASSERT (0); // We must never return from the above function
+}
+
+VOID
+TrustedWorldInitialization (
+ IN UINTN MpId,
+ IN UINTN SecBootMode
+ )
+{
+ UINTN JumpAddress;
+
+ //-------------------- Monitor Mode ---------------------
+
+ // Set up Monitor World (Vector Table, etc)
+ ArmSecureMonitorWorldInitialize ();
+
+ // Transfer the interrupt to Non-secure World
+ ArmGicV3SetupNonSecure (MpId, PcdGet64(PcdGicDistributorBase), PcdGet64(PcdGicRedistributorsBase));
+
+ // Initialize platform specific security policy
+ ArmPlatformSecTrustzoneInit (MpId);
+
+ // Setup the Trustzone Chipsets
+ if (SecBootMode == ARM_SEC_COLD_BOOT) {
+ if (ArmPlatformIsPrimaryCore (MpId)) {
+ if (ArmIsMpCore()) {
+ // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
+ ArmCallSEV ();
+ }
+ } else {
+ // The secondary cores need to wait until the Trustzone chipsets configuration is done
+ // before switching to Non Secure World
+
+ // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
+ ArmCallWFE ();
+ }
+ }
+
+ // Call the Platform specific function to execute additional actions if required
+ JumpAddress = PcdGet64 (PcdFvBaseAddress);
+
+ ArmPlatformSecExtraAction (MpId, &JumpAddress);
+
+ // Initialize architecture specific security policy
+ ArmSecArchTrustzoneInit ();
+
+ // CP15 Secure Configuration Register
+ ArmWriteScr (PcdGet32 (PcdArmScr));
+
+ NonTrustedWorldTransition (MpId, JumpAddress);
+}
+
+VOID
+NonTrustedWorldTransition (
+ IN UINTN MpId,
+ IN UINTN JumpAddress
+ )
+{
+ // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
+ // By not set, the mode for Non Secure World is SVC
+ if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
+ set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
+ }
+
+ return_from_exception (JumpAddress);
+ //-------------------- Non Secure Mode ---------------------
+
+ // PEI Core should always load and never return
+ ASSERT (FALSE);
+}
+
+/*
+ * This function configures the all interrupts to be Non-secure.
+ *
+ */
+VOID
+EFIAPI
+ArmGicV3SetupNonSecure (
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicRedistributorsBase
+ )
+{
+ UINTN InterruptId;
+ UINTN Index;
+ UINTN MaxInterrupts;
+ UINT32 WakeR;
+
+ // Set priority Mask so that no interrupts get through to CPU
+ ArmGicV3SetPriorityMask (0);
+
+ // Clear ProcessorSleep bit in GICR_WAKER and wait for ChildrenAsleep to clear
+ WakeR = MmioRead32 (GicRedistributorsBase + ARM_GICR_WAKER);
+ WakeR &= ~(1 << 1);
+ MmioWrite32 (GicRedistributorsBase + ARM_GICR_WAKER, WakeR);
+ do {
+ WakeR = MmioRead32 (GicRedistributorsBase + ARM_GICR_WAKER);
+ } while ((WakeR & (1 << 2)));
+
+ // Set PPIs to Non-secure Group 1 IRQ
+ MmioWrite32 (GicRedistributorsBase + ARM_GICR_SGI_PPI_FRAME_SIZE + ARM_GICR_IGROUPR0, 0xffff0000);
+
+ InterruptId = ArmGicV3AcknowledgeInterrupt();
+ MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);
+
+ // Only try to clear valid interrupts. Ignore spurious interrupts.
+ while ((InterruptId & 0x3FF) < MaxInterrupts) {
+ // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
+ ArmGicV3EndOfInterrupt (InterruptId);
+
+ // Next
+ InterruptId = ArmGicV3AcknowledgeInterrupt();
+ }
+
+ // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
+ if (ArmPlatformIsPrimaryCore (MpId)) {
+ // Ensure all GIC interrupts are Non-Secure
+ for (Index = 0; Index < (MaxInterrupts / 32); Index++) {
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
+ }
+ } else {
+ // The secondary cores only set the Non Secure bit to their banked PPIs
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
+ }
+
+ // Ensure all interrupts can get through the priority mask
+ ArmGicV3SetPriorityMask (0xff);
+}
+
+//
+// Previously in ArmCpuLib:
+//
+
+VOID
+ArmCpuSetup (
+ IN UINTN MpId
+ )
+{
+ // Check if Architectural Timer frequency is valid number (should not be 0)
+ ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
+ ASSERT (ArmIsArchTimerImplemented () != 0);
+
+ // Note: System Counter frequency can only be set in Secure privileged mode,
+ // if security extensions are implemented.
+ ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
+
+ if (ArmIsMpCore ()) {
+ // Turn on SMP coherency
+ ArmSetCpuExCrBit (A5X_FEATURE_SMP);
+ }
+
+ //
+ // If CPU is CortexA57 r0p0 apply Errata workarounds
+ //
+ if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
+ ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
+
+ // Errata 806969: DisableLoadStoreWB (1ULL << 49)
+ // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate (ULL << 44)
+ // Errata 814670: disable DMB nullification (1ULL << 58)
+ ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
+ }
+}
+
+VOID
+ArmCpuSetupSmpNonSecure (
+ IN UINTN MpId
+ )
+{
+}
+
+VOID
+EFIAPI
+ArmSetCpuExCrBit (
+ IN UINT64 Bits
+ )
+{
+ UINT64 Value;
+ Value = ArmReadCpuExCr ();
+ Value |= Bits;
+ ArmWriteCpuExCr (Value);
+}
+
+VOID
+EFIAPI
+ArmUnsetCpuExCrBit (
+ IN UINT64 Bits
+ )
+{
+ UINT64 Value;
+ Value = ArmReadCpuExCr ();
+ Value &= ~Bits;
+ ArmWriteCpuExCr (Value);
+}
diff --git a/CadencePkg/Sec/Sec.inf b/CadencePkg/Sec/Sec.inf
new file mode 100644
index 0000000..cf32f34
--- /dev/null
+++ b/CadencePkg/Sec/Sec.inf
@@ -0,0 +1,85 @@
+#/** @file
+# SEC - Reset vector code that jumps to C and starts the PEI phase
+#
+# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>
+# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 1.25
+ BASE_NAME = ArmPlatformSec
+ FILE_GUID = 424b4f2e-ec82-4c57-a188-253060be8a69
+ MODULE_TYPE = SEC
+ VERSION_STRING = 1.0
+
+[Sources]
+ Sec.c
+
+[Sources.AARCH64]
+ AArch64/Arch.c
+ AArch64/Helper.S
+ AArch64/SecEntryPoint.S
+ AArch64/ArmCortexA5xHelper.S | GCC
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ CadencePkg/CadenceCspPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ ArmGenericTimerCounterLib
+ ArmPlatformLib
+ ArmPlatformSecLib
+ ArmTrustedMonitorLib
+ BaseLib
+ DebugLib
+ DebugAgentLib
+ IoLib
+ ArmGicLib
+ PcdLib
+ PrintLib
+ SerialPortLib
+
+[Pcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
+
+[FixedPcd.common]
+
+ gArmTokenSpaceGuid.PcdTrustzoneSupport
+ gArmTokenSpaceGuid.PcdVFPEnabled
+
+ gArmTokenSpaceGuid.PcdArmScr
+ gArmTokenSpaceGuid.PcdArmNonSecModeTransition
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+
+ gArmTokenSpaceGuid.PcdSecureFvBaseAddress
+ gArmTokenSpaceGuid.PcdSecureFvSize
+
+ gArmTokenSpaceGuid.PcdFvBaseAddress
+
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
+
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+[FixedPcd.ARM]
+ gArmTokenSpaceGuid.PcdArmNsacr
+
diff --git a/CadencePkg/Sec/SecInternal.h b/CadencePkg/Sec/SecInternal.h
new file mode 100644
index 0000000..221eb57
--- /dev/null
+++ b/CadencePkg/Sec/SecInternal.h
@@ -0,0 +1,105 @@
+/** @file
+* Main file supporting the SEC Phase on ARM PLatforms
+*
+* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __SEC_H__
+#define __SEC_H__
+
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/ArmPlatformSecLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)
+
+VOID
+TrustedWorldInitialization (
+ IN UINTN MpId,
+ IN UINTN SecBootMode
+ );
+
+VOID
+NonTrustedWorldTransition (
+ IN UINTN MpId,
+ IN UINTN JumpAddress
+ );
+
+VOID
+ArmGicV3SetupNonSecure (
+ IN UINTN MpId,
+ IN INTN GicDistributorBase,
+ IN INTN GicRedistributorsBase
+);
+
+VOID
+enter_monitor_mode (
+ IN UINTN MonitorEntryPoint,
+ IN UINTN MpId,
+ IN UINTN SecBootMode,
+ IN VOID* MonitorStackBase
+ );
+
+VOID
+return_from_exception (
+ IN UINTN NonSecureBase
+ );
+
+VOID
+copy_cpsr_into_spsr (
+ VOID
+ );
+
+VOID
+set_non_secure_mode (
+ IN ARM_PROCESSOR_MODE Mode
+ );
+
+VOID
+SecCommonExceptionEntry (
+ IN UINT32 Entry,
+ IN UINTN LR
+ );
+
+VOID
+EFIAPI
+ArmSecArchTrustzoneInit (
+ VOID
+ );
+
+VOID
+ArmCpuSetup (
+ IN UINTN MpId
+ );
+
+VOID
+ArmCpuSetupSmpNonSecure (
+ IN UINTN MpId
+ );
+
+VOID
+EFIAPI
+ArmSetCpuExCrBit (
+ IN UINT64 Bits
+);
+
+VOID
+EFIAPI
+ArmUnsetCpuExCrBit (
+ IN UINT64 Bits
+);
+
+#endif
--
2.2.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [staging/cadence-aarch64 PATCH v3 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform.
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform Scott Telford
@ 2017-06-22 15:21 ` Leif Lindholm
2017-06-23 18:43 ` Ard Biesheuvel
0 siblings, 1 reply; 16+ messages in thread
From: Leif Lindholm @ 2017-06-22 15:21 UTC (permalink / raw)
To: Scott Telford
Cc: edk2-devel, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
On Thu, Jun 22, 2017 at 10:31:59AM +0100, Scott Telford wrote:
> Add SEC phase implementation for Cadence CSP platform configured with
> a single Cortex-A53 processor and GIC-500.
>
> Based on ArmPlatformPkg/Sec, with required parts of
> ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib integrated (both now deleted
> from edk2 master).
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford <stelford@cadence.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> CadencePkg/Sec/AArch64/Arch.c | 25 +++
> CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S | 27 +++
> CadencePkg/Sec/AArch64/Helper.S | 93 ++++++++
> CadencePkg/Sec/AArch64/SecEntryPoint.S | 139 ++++++++++++
> CadencePkg/Sec/Sec.c | 335 ++++++++++++++++++++++++++++
> CadencePkg/Sec/Sec.inf | 85 +++++++
> CadencePkg/Sec/SecInternal.h | 105 +++++++++
> 7 files changed, 809 insertions(+)
> create mode 100644 CadencePkg/Sec/AArch64/Arch.c
> create mode 100644 CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
> create mode 100644 CadencePkg/Sec/AArch64/Helper.S
> create mode 100644 CadencePkg/Sec/AArch64/SecEntryPoint.S
> create mode 100644 CadencePkg/Sec/Sec.c
> create mode 100644 CadencePkg/Sec/Sec.inf
> create mode 100644 CadencePkg/Sec/SecInternal.h
>
> diff --git a/CadencePkg/Sec/AArch64/Arch.c b/CadencePkg/Sec/AArch64/Arch.c
> new file mode 100644
> index 0000000..6e7d58e
> --- /dev/null
> +++ b/CadencePkg/Sec/AArch64/Arch.c
> @@ -0,0 +1,25 @@
> +/** @file
> +*
> +* Copyright (c) 2013, ARM Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Chipset/AArch64.h>
> +
> +VOID
> +EFIAPI
> +ArmSecArchTrustzoneInit (
> + VOID
> + )
> +{
> + // Do not trap any access to Floating Point and Advanced SIMD in EL3.
> + ArmWriteCptr (0);
> +}
> diff --git a/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
> new file mode 100644
> index 0000000..531de63
> --- /dev/null
> +++ b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
> @@ -0,0 +1,27 @@
> +#------------------------------------------------------------------------------
> +#
> +# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD Licese
> +# which accompanies this distribution. The full text of the license may be foun at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#------------------------------------------------------------------------------
> +
> +#include <AsmMacroIoLibV8.h>
> +
> +ASM_FUNC(ArmReadCpuExCr)
> + mrs x0, S3_1_c15_c2_1
> + ret
> +
> +ASM_FUNC(ArmWriteCpuExCr)
> + msr S3_1_c15_c2_1, x0
> + dsb sy
> + isb
> + ret
> +
> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> diff --git a/CadencePkg/Sec/AArch64/Helper.S b/CadencePkg/Sec/AArch64/Helper.S
> new file mode 100644
> index 0000000..3b58e12
> --- /dev/null
> +++ b/CadencePkg/Sec/AArch64/Helper.S
> @@ -0,0 +1,93 @@
> +#========================================================================================
> +# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http:#opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#=======================================================================================
> +
> +#include <AsmMacroIoLibV8.h>
> +#include <Chipset/AArch64.h>
> +
> +#start of the code section
> +.text
> +.align 3
> +
> +GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)
> +GCC_ASM_EXPORT(enter_monitor_mode)
> +GCC_ASM_EXPORT(return_from_exception)
> +GCC_ASM_EXPORT(copy_cpsr_into_spsr)
> +GCC_ASM_EXPORT(set_non_secure_mode)
> +
> +// Switch from EL3 to NS-EL1
> +ASM_PFX(SwitchToNSExceptionLevel1):
> + // Now setup our EL1. Controlled by EL2 config on Model
> + mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
> + orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
> +
> + // Send all interrupts to their respective Exception levels for EL2
> + and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort
> + msr hcr_el2, x0 // Write back our settings
> +
> + msr cptr_el2, xzr // Disable copro traps to EL2
> +
> + msr sctlr_el2, xzr
> +
> + // Enable architected timer access
> + mrs x0, cnthctl_el2
> + orr x0, x0, #3 // Enable EL1 access to timers
> + msr cnthctl_el2, x0
> +
> + mrs x0, cntkctl_el1
> + orr x0, x0, #3 // EL0 access to counters
> + msr cntkctl_el1, x0
> +
> + // Set ID regs
> + mrs x0, midr_el1
> + mrs x1, mpidr_el1
> + msr vpidr_el2, x0
> + msr vmpidr_el2, x1
> +
> + ret
> +
> +
> +// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7
> +// we don't need a mode switch, just setup the Arguments and jump.
> +// x0: Monitor World EntryPoint
> +// x1: MpId
> +// x2: SecBootMode
> +// x3: Secure Monitor mode stack
> +ASM_PFX(enter_monitor_mode):
> + mov x4, x0 // Swap EntryPoint and MpId registers
> + mov x0, x1
> + mov x1, x2
> + mov x2, x3
> + br x4
> +
> +// Put the address in correct ELR_ELx and do a eret.
> +// We may need to do some config before we change to another Mode.
> +ASM_PFX(return_from_exception):
> + msr elr_el3, x0
> + eret
> +
> +// For AArch64 we need to construct the spsr we want from individual bits and pieces.
> +ASM_PFX(copy_cpsr_into_spsr):
> + mrs x0, CurrentEl // Get the current exception level we are running at.
> + mrs x1, SPSel // Which Stack are we using
> + orr x0, x0, x1
> + mrs x1, daif // Which interrupts are enabled
> + orr x0, x0, x1
> + msr spsr_el3, x0 // Write to spsr
> + ret
> +
> +// Get this from platform file.
> +ASM_PFX(set_non_secure_mode):
> + msr spsr_el3, x0
> + ret
> +
> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
> diff --git a/CadencePkg/Sec/AArch64/SecEntryPoint.S b/CadencePkg/Sec/AArch64/SecEntryPoint.S
> new file mode 100644
> index 0000000..06bea3c
> --- /dev/null
> +++ b/CadencePkg/Sec/AArch64/SecEntryPoint.S
> @@ -0,0 +1,139 @@
> +//
> +// Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +//
> +// This program and the accompanying materials
> +// are licensed and made available under the terms and conditions of the BSD License
> +// which accompanies this distribution. The full text of the license may be found at
> +// http://opensource.org/licenses/bsd-license.php
> +//
> +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +//
> +//
> +
> +#include <AutoGen.h>
> +#include <AsmMacroIoLibV8.h>
> +#include "SecInternal.h"
> +
> +.text
> +.align 3
> +
> +GCC_ASM_IMPORT(CEntryPoint)
> +GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)
> +GCC_ASM_IMPORT(ArmPlatformGetCorePosition)
> +GCC_ASM_IMPORT(ArmPlatformSecBootAction)
> +GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
> +GCC_ASM_IMPORT(ArmDisableInterrupts)
> +GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
> +GCC_ASM_IMPORT(ArmReadMpidr)
> +GCC_ASM_IMPORT(ArmCallWFE)
> +GCC_ASM_EXPORT(_ModuleEntryPoint)
> +
> +StartupAddr: .8byte ASM_PFX(CEntryPoint)
> +
> +ASM_PFX(_ModuleEntryPoint):
> +
> +// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
> +// and configure the system accordingly. EL2 is default if possible.
> +// If we started in EL3 we need to switch and run at EL2.
> +// If we are running at EL2 stay in EL2
> +// If we are starting at EL1 stay in EL1.
> +
> +// Sec only runs in EL3. Othewise we jump to PEI without changing anything.
> +// If Sec runs we change to EL2 before switching to PEI.
> +
> +// Which EL are we running at? Every EL needs some level of setup...
> + EL1_OR_EL2_OR_EL3(x0)
> +1:// If we are at EL1 or EL2 leave SEC for PEI.
> +2:b ASM_PFX(JumpToPEI)
> + // If we are at EL3 we need to configure it and switch to EL2
> +3:b ASM_PFX(MainEntryPoint)
> +
> +ASM_PFX(MainEntryPoint):
> + // First ensure all interrupts are disabled
> + bl ASM_PFX(ArmDisableInterrupts)
> +
> + // Ensure that the MMU and caches are off
> + bl ASM_PFX(ArmDisableCachesAndMmu)
> +
> + // By default, we are doing a cold boot
> + mov x10, #ARM_SEC_COLD_BOOT
> +
> + // Jump to Platform Specific Boot Action function
> + bl ASM_PFX(ArmPlatformSecBootAction)
> +
> +_IdentifyCpu:
> + // Identify CPU ID
> + bl ASM_PFX(ArmReadMpidr)
> + // Keep a copy of the MpId register value
> + mov x5, x0
> +
> + // Is it the Primary Core ?
> + bl ASM_PFX(ArmPlatformIsPrimaryCore)
> + cmp x0, #1
> + // Only the primary core initialize the memory (SMC)
> + b.eq _InitMem
> +
> +_WaitInitMem:
> + // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
> + // Otherwise we have to wait the Primary Core to finish the initialization
> + cmp x10, #ARM_SEC_COLD_BOOT
> + b.ne _SetupSecondaryCoreStack
> +
> + // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
> + bl ASM_PFX(ArmCallWFE)
> + // Now the Init Mem is initialized, we setup the secondary core stacks
> + b _SetupSecondaryCoreStack
> +
> +_InitMem:
> + // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
> + cmp x10, #ARM_SEC_COLD_BOOT
> + b.ne _SetupPrimaryCoreStack
> +
> + // Initialize Init Boot Memory
> + bl ASM_PFX(ArmPlatformSecBootMemoryInit)
> +
> +_SetupPrimaryCoreStack:
> + // Get the top of the primary stacks (and the base of the secondary stacks)
> + MOV32 (x1, FixedPcdGet32(PcdCPUCoresSecStackBase))
> + MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize))
> + add x1, x1, x2
> +
> + mov sp, x1
> + b _PrepareArguments
> +
> +_SetupSecondaryCoreStack:
> + // Get the top of the primary stacks (and the base of the secondary stacks)
> + MOV32 (x1, FixedPcdGet32(PcdCPUCoresSecStackBase))
> + MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize))
> + add x6, x1, x2
> +
> + // Get the Core Position
> + mov x0, x5
> + bl ASM_PFX(ArmPlatformGetCorePosition)
> + // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
> + add x0, x0, #1
> +
> + // StackOffset = CorePos * StackSize
> + MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize))
> + mul x0, x0, x2
> + // SP = StackBase + StackOffset
> + add sp, x6, x0
> +
> +_PrepareArguments:
> + // Move sec startup address into a data register
> + // Ensure we're jumping to FV version of the code (not boot remapped alias)
> + ldr x3, StartupAddr
> +
> + // Jump to SEC C code
> + // r0 = mp_id
> + // r1 = Boot Mode
> + mov x0, x5
> + mov x1, x10
> + blr x3
> +
> + ret
> +
> +ASM_PFX(JumpToPEI):
> + MOV32 (x0, FixedPcdGet32(PcdFvBaseAddress))
> + blr x0
> diff --git a/CadencePkg/Sec/Sec.c b/CadencePkg/Sec/Sec.c
> new file mode 100644
> index 0000000..5b0244e
> --- /dev/null
> +++ b/CadencePkg/Sec/Sec.c
> @@ -0,0 +1,335 @@
> +/** @file
> +* Main file supporting the SEC Phase on ARM Platforms
> +*
> +* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include <Chipset/ArmCortexA5x.h>
> +#include <Library/ArmTrustedMonitorLib.h>
> +#include <Library/ArmGenericTimerCounterLib.h>
> +#include <Library/DebugAgentLib.h>
> +#include <Library/IoLib.h>
> +#include <Library/PrintLib.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/SerialPortLib.h>
> +#include <Library/ArmGicLib.h>
> +#include <Library/ArmPlatformLib.h>
> +
> +#include "SecInternal.h"
> +
> +#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
> +
> +#define ARM_GICR_WAKER 0x0014 // GIC Redistributor Wake Register
> +#define ARM_GICR_IGROUPR0 0x0080 // GIC Redistributor Int Group Reg 0
> +#define ARM_GICR_IGRPMODR0 0x0d00 // GIC Redistributor Int Group Mod Reg 0
> +#define ARM_GICR_ICFGR1 0x0c04 // GIC Redistributor Int Config Reg 0
> +
> +
> +VOID
> +CEntryPoint (
> + IN UINTN MpId,
> + IN UINTN SecBootMode
> + )
> +{
> + CHAR8 Buffer[100];
> + UINTN CharCount;
> + UINTN JumpAddress;
> +
> + // Invalidate the data cache. Doesn't have to do the Data cache clean.
> + ArmInvalidateDataCache ();
> +
> + // Invalidate Instruction Cache
> + ArmInvalidateInstructionCache ();
> +
> + // Invalidate I & D TLBs
> + ArmInvalidateTlb ();
> +
> + // CPU specific settings
> + ArmCpuSetup (MpId);
> +
> + // Enable Floating Point Coprocessor if supported by the platform
> + if (FixedPcdGet32 (PcdVFPEnabled)) {
> + ArmEnableVFP ();
> + }
> +
> + // Initialize peripherals that must be done at the early stage
> + // Example: Some L2 controller, interconnect, clock, DMC, etc
> + ArmPlatformSecInitialize (MpId);
> +
> + // Primary CPU clears out the SCU tag RAMs, secondaries wait
> + if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {
> + if (ArmIsMpCore()) {
> + // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
> + ArmCallSEV ();
> + }
> +
> + // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
> + // In non SEC modules the init call is in autogenerated code.
> + SerialPortInitialize ();
> +
> + // Start talking
> + if (FixedPcdGetBool (PcdTrustzoneSupport)) {
> + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",
> + (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
> + } else {
> + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",
> + (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
> + }
> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
> +
> + // Initialize the Debug Agent for Source Level Debugging
> + InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
> + SaveAndSetDebugTimerInterrupt (TRUE);
> +
> + // Enable the GIC distributor and CPU Interface
> + // - no other Interrupts are enabled, doesn't have to worry about the priority.
> + // - all the cores are in secure state, use secure SGI's
> + ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));
> + ArmGicEnableInterruptInterface (PcdGet64(PcdGicInterruptInterfaceBase));
> + } else {
> + // Enable the GIC CPU Interface
> + ArmGicEnableInterruptInterface (PcdGet64(PcdGicInterruptInterfaceBase));
> + }
> +
> + // Enable Full Access to CoProcessors
> + ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
> +
> + // Test if Trustzone is supported on this platform
> + if (FixedPcdGetBool (PcdTrustzoneSupport)) {
> + if (ArmIsMpCore ()) {
> + // Setup SMP in Non Secure world
> + ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
> + }
> +
> + // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
> + // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
> + ASSERT (((PcdGet64(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
> + ((PcdGet64(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
> +
> + // Enter Monitor Mode
> + enter_monitor_mode (
> + (UINTN)TrustedWorldInitialization, MpId, SecBootMode,
> + (VOID*) (PcdGet64 (PcdCPUCoresSecMonStackBase) +
> + (PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosition (MpId) + 1)))
> + );
> + } else {
> + if (ArmPlatformIsPrimaryCore (MpId)) {
> + SerialPrint ("Trust Zone Configuration is disabled\n\r");
> + }
> +
> + // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
> + // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
> + // Status Register as the the current one (CPSR).
> + copy_cpsr_into_spsr ();
> +
> + // Call the Platform specific function to execute additional actions if required
> + JumpAddress = PcdGet64 (PcdFvBaseAddress);
> +
> + ArmPlatformSecExtraAction (MpId, &JumpAddress);
> +
> + NonTrustedWorldTransition (MpId, JumpAddress);
> + }
> + ASSERT (0); // We must never return from the above function
> +}
> +
> +VOID
> +TrustedWorldInitialization (
> + IN UINTN MpId,
> + IN UINTN SecBootMode
> + )
> +{
> + UINTN JumpAddress;
> +
> + //-------------------- Monitor Mode ---------------------
> +
> + // Set up Monitor World (Vector Table, etc)
> + ArmSecureMonitorWorldInitialize ();
> +
> + // Transfer the interrupt to Non-secure World
> + ArmGicV3SetupNonSecure (MpId, PcdGet64(PcdGicDistributorBase), PcdGet64(PcdGicRedistributorsBase));
> +
> + // Initialize platform specific security policy
> + ArmPlatformSecTrustzoneInit (MpId);
> +
> + // Setup the Trustzone Chipsets
> + if (SecBootMode == ARM_SEC_COLD_BOOT) {
> + if (ArmPlatformIsPrimaryCore (MpId)) {
> + if (ArmIsMpCore()) {
> + // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
> + ArmCallSEV ();
> + }
> + } else {
> + // The secondary cores need to wait until the Trustzone chipsets configuration is done
> + // before switching to Non Secure World
> +
> + // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
> + ArmCallWFE ();
> + }
> + }
> +
> + // Call the Platform specific function to execute additional actions if required
> + JumpAddress = PcdGet64 (PcdFvBaseAddress);
> +
> + ArmPlatformSecExtraAction (MpId, &JumpAddress);
> +
> + // Initialize architecture specific security policy
> + ArmSecArchTrustzoneInit ();
> +
> + // CP15 Secure Configuration Register
> + ArmWriteScr (PcdGet32 (PcdArmScr));
> +
> + NonTrustedWorldTransition (MpId, JumpAddress);
> +}
> +
> +VOID
> +NonTrustedWorldTransition (
> + IN UINTN MpId,
> + IN UINTN JumpAddress
> + )
> +{
> + // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
> + // By not set, the mode for Non Secure World is SVC
> + if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
> + set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
> + }
> +
> + return_from_exception (JumpAddress);
> + //-------------------- Non Secure Mode ---------------------
> +
> + // PEI Core should always load and never return
> + ASSERT (FALSE);
> +}
> +
> +/*
> + * This function configures the all interrupts to be Non-secure.
> + *
> + */
> +VOID
> +EFIAPI
> +ArmGicV3SetupNonSecure (
> + IN UINTN MpId,
> + IN INTN GicDistributorBase,
> + IN INTN GicRedistributorsBase
> + )
> +{
> + UINTN InterruptId;
> + UINTN Index;
> + UINTN MaxInterrupts;
> + UINT32 WakeR;
> +
> + // Set priority Mask so that no interrupts get through to CPU
> + ArmGicV3SetPriorityMask (0);
> +
> + // Clear ProcessorSleep bit in GICR_WAKER and wait for ChildrenAsleep to clear
> + WakeR = MmioRead32 (GicRedistributorsBase + ARM_GICR_WAKER);
> + WakeR &= ~(1 << 1);
> + MmioWrite32 (GicRedistributorsBase + ARM_GICR_WAKER, WakeR);
> + do {
> + WakeR = MmioRead32 (GicRedistributorsBase + ARM_GICR_WAKER);
> + } while ((WakeR & (1 << 2)));
> +
> + // Set PPIs to Non-secure Group 1 IRQ
> + MmioWrite32 (GicRedistributorsBase + ARM_GICR_SGI_PPI_FRAME_SIZE + ARM_GICR_IGROUPR0, 0xffff0000);
> +
> + InterruptId = ArmGicV3AcknowledgeInterrupt();
> + MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);
> +
> + // Only try to clear valid interrupts. Ignore spurious interrupts.
> + while ((InterruptId & 0x3FF) < MaxInterrupts) {
> + // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
> + ArmGicV3EndOfInterrupt (InterruptId);
> +
> + // Next
> + InterruptId = ArmGicV3AcknowledgeInterrupt();
> + }
> +
> + // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
> + if (ArmPlatformIsPrimaryCore (MpId)) {
> + // Ensure all GIC interrupts are Non-Secure
> + for (Index = 0; Index < (MaxInterrupts / 32); Index++) {
> + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
> + }
> + } else {
> + // The secondary cores only set the Non Secure bit to their banked PPIs
> + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
> + }
> +
> + // Ensure all interrupts can get through the priority mask
> + ArmGicV3SetPriorityMask (0xff);
> +}
> +
> +//
> +// Previously in ArmCpuLib:
> +//
> +
> +VOID
> +ArmCpuSetup (
> + IN UINTN MpId
> + )
> +{
> + // Check if Architectural Timer frequency is valid number (should not be 0)
> + ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
> + ASSERT (ArmIsArchTimerImplemented () != 0);
> +
> + // Note: System Counter frequency can only be set in Secure privileged mode,
> + // if security extensions are implemented.
> + ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
> +
> + if (ArmIsMpCore ()) {
> + // Turn on SMP coherency
> + ArmSetCpuExCrBit (A5X_FEATURE_SMP);
> + }
> +
> + //
> + // If CPU is CortexA57 r0p0 apply Errata workarounds
> + //
> + if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
> + ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
> +
> + // Errata 806969: DisableLoadStoreWB (1ULL << 49)
> + // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate (ULL << 44)
> + // Errata 814670: disable DMB nullification (1ULL << 58)
> + ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
> + }
> +}
> +
> +VOID
> +ArmCpuSetupSmpNonSecure (
> + IN UINTN MpId
> + )
> +{
> +}
> +
> +VOID
> +EFIAPI
> +ArmSetCpuExCrBit (
> + IN UINT64 Bits
> + )
> +{
> + UINT64 Value;
> + Value = ArmReadCpuExCr ();
> + Value |= Bits;
> + ArmWriteCpuExCr (Value);
> +}
> +
> +VOID
> +EFIAPI
> +ArmUnsetCpuExCrBit (
> + IN UINT64 Bits
> + )
> +{
> + UINT64 Value;
> + Value = ArmReadCpuExCr ();
> + Value &= ~Bits;
> + ArmWriteCpuExCr (Value);
> +}
> diff --git a/CadencePkg/Sec/Sec.inf b/CadencePkg/Sec/Sec.inf
> new file mode 100644
> index 0000000..cf32f34
> --- /dev/null
> +++ b/CadencePkg/Sec/Sec.inf
> @@ -0,0 +1,85 @@
> +#/** @file
> +# SEC - Reset vector code that jumps to C and starts the PEI phase
> +#
> +# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>
> +# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +#**/
> +
> +[Defines]
> + INF_VERSION = 1.25
> + BASE_NAME = ArmPlatformSec
> + FILE_GUID = 424b4f2e-ec82-4c57-a188-253060be8a69
> + MODULE_TYPE = SEC
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + Sec.c
> +
> +[Sources.AARCH64]
> + AArch64/Arch.c
> + AArch64/Helper.S
> + AArch64/SecEntryPoint.S
> + AArch64/ArmCortexA5xHelper.S | GCC
> +
> +[Packages]
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + CadencePkg/CadenceCspPkg.dec
> +
> +[LibraryClasses]
> + ArmLib
> + ArmGenericTimerCounterLib
> + ArmPlatformLib
> + ArmPlatformSecLib
> + ArmTrustedMonitorLib
> + BaseLib
> + DebugLib
> + DebugAgentLib
> + IoLib
> + ArmGicLib
> + PcdLib
> + PrintLib
> + SerialPortLib
> +
> +[Pcd]
> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
> +
> +[FixedPcd.common]
> +
> + gArmTokenSpaceGuid.PcdTrustzoneSupport
> + gArmTokenSpaceGuid.PcdVFPEnabled
> +
> + gArmTokenSpaceGuid.PcdArmScr
> + gArmTokenSpaceGuid.PcdArmNonSecModeTransition
> + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
> +
> + gArmTokenSpaceGuid.PcdSecureFvBaseAddress
> + gArmTokenSpaceGuid.PcdSecureFvSize
> +
> + gArmTokenSpaceGuid.PcdFvBaseAddress
> +
> + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
> + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize
> + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize
> + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase
> + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
> +
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> +
> +[FixedPcd.ARM]
> + gArmTokenSpaceGuid.PcdArmNsacr
> +
> diff --git a/CadencePkg/Sec/SecInternal.h b/CadencePkg/Sec/SecInternal.h
> new file mode 100644
> index 0000000..221eb57
> --- /dev/null
> +++ b/CadencePkg/Sec/SecInternal.h
> @@ -0,0 +1,105 @@
> +/** @file
> +* Main file supporting the SEC Phase on ARM PLatforms
> +*
> +* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#ifndef __SEC_H__
> +#define __SEC_H__
> +
> +#include <Base.h>
> +#include <Library/ArmLib.h>
> +#include <Library/ArmPlatformLib.h>
> +#include <Library/ArmPlatformSecLib.h>
> +#include <Library/BaseLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/PcdLib.h>
> +
> +#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)
> +
> +VOID
> +TrustedWorldInitialization (
> + IN UINTN MpId,
> + IN UINTN SecBootMode
> + );
> +
> +VOID
> +NonTrustedWorldTransition (
> + IN UINTN MpId,
> + IN UINTN JumpAddress
> + );
> +
> +VOID
> +ArmGicV3SetupNonSecure (
> + IN UINTN MpId,
> + IN INTN GicDistributorBase,
> + IN INTN GicRedistributorsBase
> +);
> +
> +VOID
> +enter_monitor_mode (
> + IN UINTN MonitorEntryPoint,
> + IN UINTN MpId,
> + IN UINTN SecBootMode,
> + IN VOID* MonitorStackBase
> + );
> +
> +VOID
> +return_from_exception (
> + IN UINTN NonSecureBase
> + );
> +
> +VOID
> +copy_cpsr_into_spsr (
> + VOID
> + );
> +
> +VOID
> +set_non_secure_mode (
> + IN ARM_PROCESSOR_MODE Mode
> + );
> +
> +VOID
> +SecCommonExceptionEntry (
> + IN UINT32 Entry,
> + IN UINTN LR
> + );
> +
> +VOID
> +EFIAPI
> +ArmSecArchTrustzoneInit (
> + VOID
> + );
> +
> +VOID
> +ArmCpuSetup (
> + IN UINTN MpId
> + );
> +
> +VOID
> +ArmCpuSetupSmpNonSecure (
> + IN UINTN MpId
> + );
> +
> +VOID
> +EFIAPI
> +ArmSetCpuExCrBit (
> + IN UINT64 Bits
> +);
> +
> +VOID
> +EFIAPI
> +ArmUnsetCpuExCrBit (
> + IN UINT64 Bits
> +);
> +
> +#endif
> --
> 2.2.2
>
^ permalink raw reply [flat|nested] 16+ messages in thread* Re: [staging/cadence-aarch64 PATCH v3 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform.
2017-06-22 15:21 ` Leif Lindholm
@ 2017-06-23 18:43 ` Ard Biesheuvel
0 siblings, 0 replies; 16+ messages in thread
From: Ard Biesheuvel @ 2017-06-23 18:43 UTC (permalink / raw)
To: Leif Lindholm
Cc: Scott Telford, edk2-devel@lists.01.org, Graeme Gregory,
afish@apple.com, Kinney, Michael D
On 22 June 2017 at 15:21, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> On Thu, Jun 22, 2017 at 10:31:59AM +0100, Scott Telford wrote:
>> Add SEC phase implementation for Cadence CSP platform configured with
>> a single Cortex-A53 processor and GIC-500.
>>
>> Based on ArmPlatformPkg/Sec, with required parts of
>> ArmPkg/Drivers/ArmCpuLib/ArmCortexA5xLib integrated (both now deleted
>> from edk2 master).
>>
>> Contributed-under: TianoCore Contribution Agreement 1.0
>> Signed-off-by: Scott Telford <stelford@cadence.com>
>
> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>> CadencePkg/Sec/AArch64/Arch.c | 25 +++
>> CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S | 27 +++
>> CadencePkg/Sec/AArch64/Helper.S | 93 ++++++++
>> CadencePkg/Sec/AArch64/SecEntryPoint.S | 139 ++++++++++++
>> CadencePkg/Sec/Sec.c | 335 ++++++++++++++++++++++++++++
>> CadencePkg/Sec/Sec.inf | 85 +++++++
>> CadencePkg/Sec/SecInternal.h | 105 +++++++++
>> 7 files changed, 809 insertions(+)
>> create mode 100644 CadencePkg/Sec/AArch64/Arch.c
>> create mode 100644 CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
>> create mode 100644 CadencePkg/Sec/AArch64/Helper.S
>> create mode 100644 CadencePkg/Sec/AArch64/SecEntryPoint.S
>> create mode 100644 CadencePkg/Sec/Sec.c
>> create mode 100644 CadencePkg/Sec/Sec.inf
>> create mode 100644 CadencePkg/Sec/SecInternal.h
>>
>> diff --git a/CadencePkg/Sec/AArch64/Arch.c b/CadencePkg/Sec/AArch64/Arch.c
>> new file mode 100644
>> index 0000000..6e7d58e
>> --- /dev/null
>> +++ b/CadencePkg/Sec/AArch64/Arch.c
>> @@ -0,0 +1,25 @@
>> +/** @file
>> +*
>> +* Copyright (c) 2013, ARM Limited. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#include <Chipset/AArch64.h>
>> +
>> +VOID
>> +EFIAPI
>> +ArmSecArchTrustzoneInit (
>> + VOID
>> + )
>> +{
>> + // Do not trap any access to Floating Point and Advanced SIMD in EL3.
>> + ArmWriteCptr (0);
>> +}
>> diff --git a/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
>> new file mode 100644
>> index 0000000..531de63
>> --- /dev/null
>> +++ b/CadencePkg/Sec/AArch64/ArmCortexA5xHelper.S
>> @@ -0,0 +1,27 @@
>> +#------------------------------------------------------------------------------
>> +#
>> +# Copyright (c) 2013 - 2014, ARM Limited. All rights reserved.
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD Licese
>> +# which accompanies this distribution. The full text of the license may be foun at
>> +# http://opensource.org/licenses/bsd-license.php
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#------------------------------------------------------------------------------
>> +
>> +#include <AsmMacroIoLibV8.h>
>> +
>> +ASM_FUNC(ArmReadCpuExCr)
>> + mrs x0, S3_1_c15_c2_1
>> + ret
>> +
>> +ASM_FUNC(ArmWriteCpuExCr)
>> + msr S3_1_c15_c2_1, x0
>> + dsb sy
>> + isb
>> + ret
>> +
>> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
>> diff --git a/CadencePkg/Sec/AArch64/Helper.S b/CadencePkg/Sec/AArch64/Helper.S
>> new file mode 100644
>> index 0000000..3b58e12
>> --- /dev/null
>> +++ b/CadencePkg/Sec/AArch64/Helper.S
>> @@ -0,0 +1,93 @@
>> +#========================================================================================
>> +# Copyright (c) 2011-2014, ARM Limited. All rights reserved.
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http:#opensource.org/licenses/bsd-license.php
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#=======================================================================================
>> +
>> +#include <AsmMacroIoLibV8.h>
>> +#include <Chipset/AArch64.h>
>> +
>> +#start of the code section
>> +.text
>> +.align 3
>> +
>> +GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)
>> +GCC_ASM_EXPORT(enter_monitor_mode)
>> +GCC_ASM_EXPORT(return_from_exception)
>> +GCC_ASM_EXPORT(copy_cpsr_into_spsr)
>> +GCC_ASM_EXPORT(set_non_secure_mode)
>> +
>> +// Switch from EL3 to NS-EL1
>> +ASM_PFX(SwitchToNSExceptionLevel1):
>> + // Now setup our EL1. Controlled by EL2 config on Model
>> + mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register
>> + orr x0, x0, #(1 << 31) // Set EL1 to be 64bit
>> +
>> + // Send all interrupts to their respective Exception levels for EL2
>> + and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort
>> + msr hcr_el2, x0 // Write back our settings
>> +
>> + msr cptr_el2, xzr // Disable copro traps to EL2
>> +
>> + msr sctlr_el2, xzr
>> +
>> + // Enable architected timer access
>> + mrs x0, cnthctl_el2
>> + orr x0, x0, #3 // Enable EL1 access to timers
>> + msr cnthctl_el2, x0
>> +
>> + mrs x0, cntkctl_el1
>> + orr x0, x0, #3 // EL0 access to counters
>> + msr cntkctl_el1, x0
>> +
>> + // Set ID regs
>> + mrs x0, midr_el1
>> + mrs x1, mpidr_el1
>> + msr vpidr_el2, x0
>> + msr vmpidr_el2, x1
>> +
>> + ret
>> +
>> +
>> +// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7
>> +// we don't need a mode switch, just setup the Arguments and jump.
>> +// x0: Monitor World EntryPoint
>> +// x1: MpId
>> +// x2: SecBootMode
>> +// x3: Secure Monitor mode stack
>> +ASM_PFX(enter_monitor_mode):
>> + mov x4, x0 // Swap EntryPoint and MpId registers
>> + mov x0, x1
>> + mov x1, x2
>> + mov x2, x3
>> + br x4
>> +
>> +// Put the address in correct ELR_ELx and do a eret.
>> +// We may need to do some config before we change to another Mode.
>> +ASM_PFX(return_from_exception):
>> + msr elr_el3, x0
>> + eret
>> +
>> +// For AArch64 we need to construct the spsr we want from individual bits and pieces.
>> +ASM_PFX(copy_cpsr_into_spsr):
>> + mrs x0, CurrentEl // Get the current exception level we are running at.
>> + mrs x1, SPSel // Which Stack are we using
>> + orr x0, x0, x1
>> + mrs x1, daif // Which interrupts are enabled
>> + orr x0, x0, x1
>> + msr spsr_el3, x0 // Write to spsr
>> + ret
>> +
>> +// Get this from platform file.
>> +ASM_PFX(set_non_secure_mode):
>> + msr spsr_el3, x0
>> + ret
>> +
>> +ASM_FUNCTION_REMOVE_IF_UNREFERENCED
>> diff --git a/CadencePkg/Sec/AArch64/SecEntryPoint.S b/CadencePkg/Sec/AArch64/SecEntryPoint.S
>> new file mode 100644
>> index 0000000..06bea3c
>> --- /dev/null
>> +++ b/CadencePkg/Sec/AArch64/SecEntryPoint.S
>> @@ -0,0 +1,139 @@
>> +//
>> +// Copyright (c) 2011-2014, ARM Limited. All rights reserved.
>> +//
>> +// This program and the accompanying materials
>> +// are licensed and made available under the terms and conditions of the BSD License
>> +// which accompanies this distribution. The full text of the license may be found at
>> +// http://opensource.org/licenses/bsd-license.php
>> +//
>> +// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +//
>> +//
>> +
>> +#include <AutoGen.h>
>> +#include <AsmMacroIoLibV8.h>
>> +#include "SecInternal.h"
>> +
>> +.text
>> +.align 3
>> +
>> +GCC_ASM_IMPORT(CEntryPoint)
>> +GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)
>> +GCC_ASM_IMPORT(ArmPlatformGetCorePosition)
>> +GCC_ASM_IMPORT(ArmPlatformSecBootAction)
>> +GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)
>> +GCC_ASM_IMPORT(ArmDisableInterrupts)
>> +GCC_ASM_IMPORT(ArmDisableCachesAndMmu)
>> +GCC_ASM_IMPORT(ArmReadMpidr)
>> +GCC_ASM_IMPORT(ArmCallWFE)
>> +GCC_ASM_EXPORT(_ModuleEntryPoint)
>> +
>> +StartupAddr: .8byte ASM_PFX(CEntryPoint)
>> +
>> +ASM_PFX(_ModuleEntryPoint):
>> +
>> +// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect
>> +// and configure the system accordingly. EL2 is default if possible.
>> +// If we started in EL3 we need to switch and run at EL2.
>> +// If we are running at EL2 stay in EL2
>> +// If we are starting at EL1 stay in EL1.
>> +
>> +// Sec only runs in EL3. Othewise we jump to PEI without changing anything.
>> +// If Sec runs we change to EL2 before switching to PEI.
>> +
>> +// Which EL are we running at? Every EL needs some level of setup...
>> + EL1_OR_EL2_OR_EL3(x0)
>> +1:// If we are at EL1 or EL2 leave SEC for PEI.
>> +2:b ASM_PFX(JumpToPEI)
>> + // If we are at EL3 we need to configure it and switch to EL2
>> +3:b ASM_PFX(MainEntryPoint)
>> +
>> +ASM_PFX(MainEntryPoint):
>> + // First ensure all interrupts are disabled
>> + bl ASM_PFX(ArmDisableInterrupts)
>> +
>> + // Ensure that the MMU and caches are off
>> + bl ASM_PFX(ArmDisableCachesAndMmu)
>> +
>> + // By default, we are doing a cold boot
>> + mov x10, #ARM_SEC_COLD_BOOT
>> +
>> + // Jump to Platform Specific Boot Action function
>> + bl ASM_PFX(ArmPlatformSecBootAction)
>> +
>> +_IdentifyCpu:
>> + // Identify CPU ID
>> + bl ASM_PFX(ArmReadMpidr)
>> + // Keep a copy of the MpId register value
>> + mov x5, x0
>> +
>> + // Is it the Primary Core ?
>> + bl ASM_PFX(ArmPlatformIsPrimaryCore)
>> + cmp x0, #1
>> + // Only the primary core initialize the memory (SMC)
>> + b.eq _InitMem
>> +
>> +_WaitInitMem:
>> + // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
>> + // Otherwise we have to wait the Primary Core to finish the initialization
>> + cmp x10, #ARM_SEC_COLD_BOOT
>> + b.ne _SetupSecondaryCoreStack
>> +
>> + // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)
>> + bl ASM_PFX(ArmCallWFE)
>> + // Now the Init Mem is initialized, we setup the secondary core stacks
>> + b _SetupSecondaryCoreStack
>> +
>> +_InitMem:
>> + // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized
>> + cmp x10, #ARM_SEC_COLD_BOOT
>> + b.ne _SetupPrimaryCoreStack
>> +
>> + // Initialize Init Boot Memory
>> + bl ASM_PFX(ArmPlatformSecBootMemoryInit)
>> +
>> +_SetupPrimaryCoreStack:
>> + // Get the top of the primary stacks (and the base of the secondary stacks)
>> + MOV32 (x1, FixedPcdGet32(PcdCPUCoresSecStackBase))
>> + MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize))
>> + add x1, x1, x2
>> +
>> + mov sp, x1
>> + b _PrepareArguments
>> +
>> +_SetupSecondaryCoreStack:
>> + // Get the top of the primary stacks (and the base of the secondary stacks)
>> + MOV32 (x1, FixedPcdGet32(PcdCPUCoresSecStackBase))
>> + MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize))
>> + add x6, x1, x2
>> +
>> + // Get the Core Position
>> + mov x0, x5
>> + bl ASM_PFX(ArmPlatformGetCorePosition)
>> + // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack
>> + add x0, x0, #1
>> +
>> + // StackOffset = CorePos * StackSize
>> + MOV32 (x2, FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize))
>> + mul x0, x0, x2
>> + // SP = StackBase + StackOffset
>> + add sp, x6, x0
>> +
>> +_PrepareArguments:
>> + // Move sec startup address into a data register
>> + // Ensure we're jumping to FV version of the code (not boot remapped alias)
>> + ldr x3, StartupAddr
>> +
>> + // Jump to SEC C code
>> + // r0 = mp_id
>> + // r1 = Boot Mode
>> + mov x0, x5
>> + mov x1, x10
>> + blr x3
>> +
>> + ret
>> +
>> +ASM_PFX(JumpToPEI):
>> + MOV32 (x0, FixedPcdGet32(PcdFvBaseAddress))
>> + blr x0
>> diff --git a/CadencePkg/Sec/Sec.c b/CadencePkg/Sec/Sec.c
>> new file mode 100644
>> index 0000000..5b0244e
>> --- /dev/null
>> +++ b/CadencePkg/Sec/Sec.c
>> @@ -0,0 +1,335 @@
>> +/** @file
>> +* Main file supporting the SEC Phase on ARM Platforms
>> +*
>> +* Copyright (c) 2011-2014, ARM Limited. All rights reserved.
>> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#include <Chipset/ArmCortexA5x.h>
>> +#include <Library/ArmTrustedMonitorLib.h>
>> +#include <Library/ArmGenericTimerCounterLib.h>
>> +#include <Library/DebugAgentLib.h>
>> +#include <Library/IoLib.h>
>> +#include <Library/PrintLib.h>
>> +#include <Library/BaseMemoryLib.h>
>> +#include <Library/SerialPortLib.h>
>> +#include <Library/ArmGicLib.h>
>> +#include <Library/ArmPlatformLib.h>
>> +
>> +#include "SecInternal.h"
>> +
>> +#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);
>> +
>> +#define ARM_GICR_WAKER 0x0014 // GIC Redistributor Wake Register
>> +#define ARM_GICR_IGROUPR0 0x0080 // GIC Redistributor Int Group Reg 0
>> +#define ARM_GICR_IGRPMODR0 0x0d00 // GIC Redistributor Int Group Mod Reg 0
>> +#define ARM_GICR_ICFGR1 0x0c04 // GIC Redistributor Int Config Reg 0
>> +
>> +
>> +VOID
>> +CEntryPoint (
>> + IN UINTN MpId,
>> + IN UINTN SecBootMode
>> + )
>> +{
>> + CHAR8 Buffer[100];
>> + UINTN CharCount;
>> + UINTN JumpAddress;
>> +
>> + // Invalidate the data cache. Doesn't have to do the Data cache clean.
>> + ArmInvalidateDataCache ();
>> +
>> + // Invalidate Instruction Cache
>> + ArmInvalidateInstructionCache ();
>> +
>> + // Invalidate I & D TLBs
>> + ArmInvalidateTlb ();
>> +
>> + // CPU specific settings
>> + ArmCpuSetup (MpId);
>> +
>> + // Enable Floating Point Coprocessor if supported by the platform
>> + if (FixedPcdGet32 (PcdVFPEnabled)) {
>> + ArmEnableVFP ();
>> + }
>> +
>> + // Initialize peripherals that must be done at the early stage
>> + // Example: Some L2 controller, interconnect, clock, DMC, etc
>> + ArmPlatformSecInitialize (MpId);
>> +
>> + // Primary CPU clears out the SCU tag RAMs, secondaries wait
>> + if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {
>> + if (ArmIsMpCore()) {
>> + // Signal for the initial memory is configured (event: BOOT_MEM_INIT)
>> + ArmCallSEV ();
>> + }
>> +
>> + // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib
>> + // In non SEC modules the init call is in autogenerated code.
>> + SerialPortInitialize ();
>> +
>> + // Start talking
>> + if (FixedPcdGetBool (PcdTrustzoneSupport)) {
>> + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",
>> + (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
>> + } else {
>> + CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",
>> + (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);
>> + }
>> + SerialPortWrite ((UINT8 *) Buffer, CharCount);
>> +
>> + // Initialize the Debug Agent for Source Level Debugging
>> + InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);
>> + SaveAndSetDebugTimerInterrupt (TRUE);
>> +
>> + // Enable the GIC distributor and CPU Interface
>> + // - no other Interrupts are enabled, doesn't have to worry about the priority.
>> + // - all the cores are in secure state, use secure SGI's
>> + ArmGicEnableDistributor (PcdGet64(PcdGicDistributorBase));
>> + ArmGicEnableInterruptInterface (PcdGet64(PcdGicInterruptInterfaceBase));
>> + } else {
>> + // Enable the GIC CPU Interface
>> + ArmGicEnableInterruptInterface (PcdGet64(PcdGicInterruptInterfaceBase));
>> + }
>> +
>> + // Enable Full Access to CoProcessors
>> + ArmWriteCpacr (CPACR_CP_FULL_ACCESS);
>> +
>> + // Test if Trustzone is supported on this platform
>> + if (FixedPcdGetBool (PcdTrustzoneSupport)) {
>> + if (ArmIsMpCore ()) {
>> + // Setup SMP in Non Secure world
>> + ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));
>> + }
>> +
>> + // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))
>> + // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))
>> + ASSERT (((PcdGet64(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||
>> + ((PcdGet64(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));
>> +
>> + // Enter Monitor Mode
>> + enter_monitor_mode (
>> + (UINTN)TrustedWorldInitialization, MpId, SecBootMode,
>> + (VOID*) (PcdGet64 (PcdCPUCoresSecMonStackBase) +
>> + (PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosition (MpId) + 1)))
>> + );
>> + } else {
>> + if (ArmPlatformIsPrimaryCore (MpId)) {
>> + SerialPrint ("Trust Zone Configuration is disabled\n\r");
>> + }
>> +
>> + // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
>> + // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
>> + // Status Register as the the current one (CPSR).
>> + copy_cpsr_into_spsr ();
>> +
>> + // Call the Platform specific function to execute additional actions if required
>> + JumpAddress = PcdGet64 (PcdFvBaseAddress);
>> +
>> + ArmPlatformSecExtraAction (MpId, &JumpAddress);
>> +
>> + NonTrustedWorldTransition (MpId, JumpAddress);
>> + }
>> + ASSERT (0); // We must never return from the above function
>> +}
>> +
>> +VOID
>> +TrustedWorldInitialization (
>> + IN UINTN MpId,
>> + IN UINTN SecBootMode
>> + )
>> +{
>> + UINTN JumpAddress;
>> +
>> + //-------------------- Monitor Mode ---------------------
>> +
>> + // Set up Monitor World (Vector Table, etc)
>> + ArmSecureMonitorWorldInitialize ();
>> +
>> + // Transfer the interrupt to Non-secure World
>> + ArmGicV3SetupNonSecure (MpId, PcdGet64(PcdGicDistributorBase), PcdGet64(PcdGicRedistributorsBase));
>> +
>> + // Initialize platform specific security policy
>> + ArmPlatformSecTrustzoneInit (MpId);
>> +
>> + // Setup the Trustzone Chipsets
>> + if (SecBootMode == ARM_SEC_COLD_BOOT) {
>> + if (ArmPlatformIsPrimaryCore (MpId)) {
>> + if (ArmIsMpCore()) {
>> + // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)
>> + ArmCallSEV ();
>> + }
>> + } else {
>> + // The secondary cores need to wait until the Trustzone chipsets configuration is done
>> + // before switching to Non Secure World
>> +
>> + // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)
>> + ArmCallWFE ();
>> + }
>> + }
>> +
>> + // Call the Platform specific function to execute additional actions if required
>> + JumpAddress = PcdGet64 (PcdFvBaseAddress);
>> +
>> + ArmPlatformSecExtraAction (MpId, &JumpAddress);
>> +
>> + // Initialize architecture specific security policy
>> + ArmSecArchTrustzoneInit ();
>> +
>> + // CP15 Secure Configuration Register
>> + ArmWriteScr (PcdGet32 (PcdArmScr));
>> +
>> + NonTrustedWorldTransition (MpId, JumpAddress);
>> +}
>> +
>> +VOID
>> +NonTrustedWorldTransition (
>> + IN UINTN MpId,
>> + IN UINTN JumpAddress
>> + )
>> +{
>> + // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition
>> + // By not set, the mode for Non Secure World is SVC
>> + if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {
>> + set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));
>> + }
>> +
>> + return_from_exception (JumpAddress);
>> + //-------------------- Non Secure Mode ---------------------
>> +
>> + // PEI Core should always load and never return
>> + ASSERT (FALSE);
>> +}
>> +
>> +/*
>> + * This function configures the all interrupts to be Non-secure.
>> + *
>> + */
>> +VOID
>> +EFIAPI
>> +ArmGicV3SetupNonSecure (
>> + IN UINTN MpId,
>> + IN INTN GicDistributorBase,
>> + IN INTN GicRedistributorsBase
>> + )
>> +{
>> + UINTN InterruptId;
>> + UINTN Index;
>> + UINTN MaxInterrupts;
>> + UINT32 WakeR;
>> +
>> + // Set priority Mask so that no interrupts get through to CPU
>> + ArmGicV3SetPriorityMask (0);
>> +
>> + // Clear ProcessorSleep bit in GICR_WAKER and wait for ChildrenAsleep to clear
>> + WakeR = MmioRead32 (GicRedistributorsBase + ARM_GICR_WAKER);
>> + WakeR &= ~(1 << 1);
>> + MmioWrite32 (GicRedistributorsBase + ARM_GICR_WAKER, WakeR);
>> + do {
>> + WakeR = MmioRead32 (GicRedistributorsBase + ARM_GICR_WAKER);
>> + } while ((WakeR & (1 << 2)));
>> +
>> + // Set PPIs to Non-secure Group 1 IRQ
>> + MmioWrite32 (GicRedistributorsBase + ARM_GICR_SGI_PPI_FRAME_SIZE + ARM_GICR_IGROUPR0, 0xffff0000);
>> +
>> + InterruptId = ArmGicV3AcknowledgeInterrupt();
>> + MaxInterrupts = ArmGicGetMaxNumInterrupts (GicDistributorBase);
>> +
>> + // Only try to clear valid interrupts. Ignore spurious interrupts.
>> + while ((InterruptId & 0x3FF) < MaxInterrupts) {
>> + // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
>> + ArmGicV3EndOfInterrupt (InterruptId);
>> +
>> + // Next
>> + InterruptId = ArmGicV3AcknowledgeInterrupt();
>> + }
>> +
>> + // Only the primary core should set the Non Secure bit to the SPIs (Shared Peripheral Interrupt).
>> + if (ArmPlatformIsPrimaryCore (MpId)) {
>> + // Ensure all GIC interrupts are Non-Secure
>> + for (Index = 0; Index < (MaxInterrupts / 32); Index++) {
>> + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + (Index * 4), 0xffffffff);
>> + }
>> + } else {
>> + // The secondary cores only set the Non Secure bit to their banked PPIs
>> + MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff);
>> + }
>> +
>> + // Ensure all interrupts can get through the priority mask
>> + ArmGicV3SetPriorityMask (0xff);
>> +}
>> +
>> +//
>> +// Previously in ArmCpuLib:
>> +//
>> +
>> +VOID
>> +ArmCpuSetup (
>> + IN UINTN MpId
>> + )
>> +{
>> + // Check if Architectural Timer frequency is valid number (should not be 0)
>> + ASSERT (PcdGet32 (PcdArmArchTimerFreqInHz));
>> + ASSERT (ArmIsArchTimerImplemented () != 0);
>> +
>> + // Note: System Counter frequency can only be set in Secure privileged mode,
>> + // if security extensions are implemented.
>> + ArmGenericTimerSetTimerFreq (PcdGet32 (PcdArmArchTimerFreqInHz));
>> +
>> + if (ArmIsMpCore ()) {
>> + // Turn on SMP coherency
>> + ArmSetCpuExCrBit (A5X_FEATURE_SMP);
>> + }
>> +
>> + //
>> + // If CPU is CortexA57 r0p0 apply Errata workarounds
>> + //
>> + if ((ArmReadMidr () & ((ARM_CPU_TYPE_MASK << 4) | ARM_CPU_REV_MASK)) ==
>> + ((ARM_CPU_TYPE_A57 << 4) | ARM_CPU_REV(0,0))) {
>> +
>> + // Errata 806969: DisableLoadStoreWB (1ULL << 49)
>> + // Errata 813420: Execute Data Cache clean as Data Cache clean/invalidate (ULL << 44)
>> + // Errata 814670: disable DMB nullification (1ULL << 58)
>> + ArmSetCpuActlrBit ( (1ULL << 49) | (1ULL << 44) | (1ULL << 58) );
>> + }
>> +}
>> +
>> +VOID
>> +ArmCpuSetupSmpNonSecure (
>> + IN UINTN MpId
>> + )
>> +{
>> +}
>> +
>> +VOID
>> +EFIAPI
>> +ArmSetCpuExCrBit (
>> + IN UINT64 Bits
>> + )
>> +{
>> + UINT64 Value;
>> + Value = ArmReadCpuExCr ();
>> + Value |= Bits;
>> + ArmWriteCpuExCr (Value);
>> +}
>> +
>> +VOID
>> +EFIAPI
>> +ArmUnsetCpuExCrBit (
>> + IN UINT64 Bits
>> + )
>> +{
>> + UINT64 Value;
>> + Value = ArmReadCpuExCr ();
>> + Value &= ~Bits;
>> + ArmWriteCpuExCr (Value);
>> +}
>> diff --git a/CadencePkg/Sec/Sec.inf b/CadencePkg/Sec/Sec.inf
>> new file mode 100644
>> index 0000000..cf32f34
>> --- /dev/null
>> +++ b/CadencePkg/Sec/Sec.inf
>> @@ -0,0 +1,85 @@
>> +#/** @file
>> +# SEC - Reset vector code that jumps to C and starts the PEI phase
>> +#
>> +# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>
>> +# Copyright (c) 2011-2013, ARM Limited. All rights reserved.
>> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
>> +#
>> +# This program and the accompanying materials
>> +# are licensed and made available under the terms and conditions of the BSD License
>> +# which accompanies this distribution. The full text of the license may be found at
>> +# http://opensource.org/licenses/bsd-license.php
>> +#
>> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +#
>> +#**/
>> +
>> +[Defines]
>> + INF_VERSION = 1.25
>> + BASE_NAME = ArmPlatformSec
>> + FILE_GUID = 424b4f2e-ec82-4c57-a188-253060be8a69
>> + MODULE_TYPE = SEC
>> + VERSION_STRING = 1.0
>> +
>> +[Sources]
>> + Sec.c
>> +
>> +[Sources.AARCH64]
>> + AArch64/Arch.c
>> + AArch64/Helper.S
>> + AArch64/SecEntryPoint.S
>> + AArch64/ArmCortexA5xHelper.S | GCC
>> +
>> +[Packages]
>> + MdePkg/MdePkg.dec
>> + MdeModulePkg/MdeModulePkg.dec
>> + ArmPkg/ArmPkg.dec
>> + ArmPlatformPkg/ArmPlatformPkg.dec
>> + CadencePkg/CadenceCspPkg.dec
>> +
>> +[LibraryClasses]
>> + ArmLib
>> + ArmGenericTimerCounterLib
>> + ArmPlatformLib
>> + ArmPlatformSecLib
>> + ArmTrustedMonitorLib
>> + BaseLib
>> + DebugLib
>> + DebugAgentLib
>> + IoLib
>> + ArmGicLib
>> + PcdLib
>> + PrintLib
>> + SerialPortLib
>> +
>> +[Pcd]
>> + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString
>> +
>> +[FixedPcd.common]
>> +
>> + gArmTokenSpaceGuid.PcdTrustzoneSupport
>> + gArmTokenSpaceGuid.PcdVFPEnabled
>> +
>> + gArmTokenSpaceGuid.PcdArmScr
>> + gArmTokenSpaceGuid.PcdArmNonSecModeTransition
>> + gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
>> +
>> + gArmTokenSpaceGuid.PcdSecureFvBaseAddress
>> + gArmTokenSpaceGuid.PcdSecureFvSize
>> +
>> + gArmTokenSpaceGuid.PcdFvBaseAddress
>> +
>> + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase
>> + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize
>> + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize
>> + gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase
>> + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize
>> +
>> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
>> + gArmTokenSpaceGuid.PcdGicDistributorBase
>> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
>> +
>> +[FixedPcd.ARM]
>> + gArmTokenSpaceGuid.PcdArmNsacr
>> +
>> diff --git a/CadencePkg/Sec/SecInternal.h b/CadencePkg/Sec/SecInternal.h
>> new file mode 100644
>> index 0000000..221eb57
>> --- /dev/null
>> +++ b/CadencePkg/Sec/SecInternal.h
>> @@ -0,0 +1,105 @@
>> +/** @file
>> +* Main file supporting the SEC Phase on ARM PLatforms
>> +*
>> +* Copyright (c) 2011-2013, ARM Limited. All rights reserved.
>> +*
>> +* This program and the accompanying materials
>> +* are licensed and made available under the terms and conditions of the BSD License
>> +* which accompanies this distribution. The full text of the license may be found at
>> +* http://opensource.org/licenses/bsd-license.php
>> +*
>> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
>> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
>> +*
>> +**/
>> +
>> +#ifndef __SEC_H__
>> +#define __SEC_H__
>> +
>> +#include <Base.h>
>> +#include <Library/ArmLib.h>
>> +#include <Library/ArmPlatformLib.h>
>> +#include <Library/ArmPlatformSecLib.h>
>> +#include <Library/BaseLib.h>
>> +#include <Library/DebugLib.h>
>> +#include <Library/PcdLib.h>
>> +
>> +#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)
>> +
>> +VOID
>> +TrustedWorldInitialization (
>> + IN UINTN MpId,
>> + IN UINTN SecBootMode
>> + );
>> +
>> +VOID
>> +NonTrustedWorldTransition (
>> + IN UINTN MpId,
>> + IN UINTN JumpAddress
>> + );
>> +
>> +VOID
>> +ArmGicV3SetupNonSecure (
>> + IN UINTN MpId,
>> + IN INTN GicDistributorBase,
>> + IN INTN GicRedistributorsBase
>> +);
>> +
>> +VOID
>> +enter_monitor_mode (
>> + IN UINTN MonitorEntryPoint,
>> + IN UINTN MpId,
>> + IN UINTN SecBootMode,
>> + IN VOID* MonitorStackBase
>> + );
>> +
>> +VOID
>> +return_from_exception (
>> + IN UINTN NonSecureBase
>> + );
>> +
>> +VOID
>> +copy_cpsr_into_spsr (
>> + VOID
>> + );
>> +
>> +VOID
>> +set_non_secure_mode (
>> + IN ARM_PROCESSOR_MODE Mode
>> + );
>> +
>> +VOID
>> +SecCommonExceptionEntry (
>> + IN UINT32 Entry,
>> + IN UINTN LR
>> + );
>> +
>> +VOID
>> +EFIAPI
>> +ArmSecArchTrustzoneInit (
>> + VOID
>> + );
>> +
>> +VOID
>> +ArmCpuSetup (
>> + IN UINTN MpId
>> + );
>> +
>> +VOID
>> +ArmCpuSetupSmpNonSecure (
>> + IN UINTN MpId
>> + );
>> +
>> +VOID
>> +EFIAPI
>> +ArmSetCpuExCrBit (
>> + IN UINT64 Bits
>> +);
>> +
>> +VOID
>> +EFIAPI
>> +ArmUnsetCpuExCrBit (
>> + IN UINT64 Bits
>> +);
>> +
>> +#endif
>> --
>> 2.2.2
>>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [staging/cadence-aarch64 PATCH v3 5/6] CadencePkg: Add ACPI tables for Cadence CSP platform.
2017-06-22 9:31 [staging/cadence-aarch64 PATCH v3 0/6] CadencePkg: Add package for Cadence hardware IP support Scott Telford
` (3 preceding siblings ...)
2017-06-22 9:31 ` [staging/cadence-aarch64 PATCH v3 4/6] CadencePkg: Add SEC phase implementation for Cadence CSP platform Scott Telford
@ 2017-06-22 9:32 ` Scott Telford
2017-06-29 16:17 ` Leif Lindholm
2017-06-22 9:32 ` [staging/cadence-aarch64 PATCH v3 6/6] CadencePkg: Add .dsc, .fdf and .dec files " Scott Telford
5 siblings, 1 reply; 16+ messages in thread
From: Scott Telford @ 2017-06-22 9:32 UTC (permalink / raw)
To: edk2-devel, leif.lindholm, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
Add ACPI tables for Cadence CSP platform configured with a single
Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford <stelford@cadence.com>
---
CadencePkg/AcpiTables/AcpiTables.inf | 50 ++++++
CadencePkg/AcpiTables/CspPlatform.h | 46 ++++++
CadencePkg/AcpiTables/Dsdt.asl | 307 +++++++++++++++++++++++++++++++++++
CadencePkg/AcpiTables/Fadt.aslc | 87 ++++++++++
CadencePkg/AcpiTables/Gtdt.aslc | 80 +++++++++
CadencePkg/AcpiTables/Madt.aslc | 71 ++++++++
CadencePkg/AcpiTables/Mcfg.aslc | 76 +++++++++
7 files changed, 717 insertions(+)
create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf
create mode 100644 CadencePkg/AcpiTables/CspPlatform.h
create mode 100644 CadencePkg/AcpiTables/Dsdt.asl
create mode 100644 CadencePkg/AcpiTables/Fadt.aslc
create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc
create mode 100644 CadencePkg/AcpiTables/Madt.aslc
create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc
diff --git a/CadencePkg/AcpiTables/AcpiTables.inf b/CadencePkg/AcpiTables/AcpiTables.inf
new file mode 100644
index 0000000..4f79485
--- /dev/null
+++ b/CadencePkg/AcpiTables/AcpiTables.inf
@@ -0,0 +1,50 @@
+## @file
+#
+# ACPI table data and ASL sources required to boot the platform.
+#
+# Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = CspAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+
+[Sources]
+ Dsdt.asl
+ Fadt.aslc
+ Gtdt.aslc
+ Madt.aslc
+ Mcfg.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ CadencePkg/CadenceCspPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gCadenceCspTokenSpaceGuid.PcdCspSerialBase
+ gCadenceCspTokenSpaceGuid.PcdCspSerialSize
diff --git a/CadencePkg/AcpiTables/CspPlatform.h b/CadencePkg/AcpiTables/CspPlatform.h
new file mode 100644
index 0000000..d3afe9e
--- /dev/null
+++ b/CadencePkg/AcpiTables/CspPlatform.h
@@ -0,0 +1,46 @@
+/** @file
+*
+* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2015, Linaro Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*
+**/
+
+
+#ifndef _CSP_PLATFORM_H_
+#define _CSP_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_CSP_OEM_ID 'C','D','N','S',' ',' ' // OEMID 6 bytes long
+#define EFI_ACPI_CSP_OEM_TABLE_ID SIGNATURE_64('C','S','P',' ',' ',' ',' ',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_CSP_OEM_REVISION 0x00000002
+#define EFI_ACPI_CSP_CREATOR_ID SIGNATURE_32('C','D','N','S')
+#define EFI_ACPI_CSP_CREATOR_REVISION 0x00000001
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
+ Signature, /* UINT32 Signature */ \
+ sizeof (Type), /* UINT32 Length */ \
+ Revision, /* UINT8 Revision */ \
+ 0, /* UINT8 Checksum */ \
+ { EFI_ACPI_CSP_OEM_ID }, /* UINT8 OemId[6] */ \
+ EFI_ACPI_CSP_OEM_TABLE_ID, /* UINT64 OemTableId */ \
+ EFI_ACPI_CSP_OEM_REVISION, /* UINT32 OemRevision */ \
+ EFI_ACPI_CSP_CREATOR_ID, /* UINT32 CreatorId */ \
+ EFI_ACPI_CSP_CREATOR_REVISION /* UINT32 CreatorRevision */ \
+ }
+
+#endif
diff --git a/CadencePkg/AcpiTables/Dsdt.asl b/CadencePkg/AcpiTables/Dsdt.asl
new file mode 100644
index 0000000..268777d
--- /dev/null
+++ b/CadencePkg/AcpiTables/Dsdt.asl
@@ -0,0 +1,307 @@
+/*
+* Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+* All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*
+*
+* NB: This License is also known as the "BSD 2-Clause License".
+*
+*
+*
+*/
+
+DefinitionBlock (
+ "dsdt.aml", // output filename
+ "DSDT", // table signature
+ 2, // DSDT compliance revision
+ "CDNS", // OEM ID
+ "CDNSCSP0", // table ID
+ 0x00000001) // OEM revision
+{
+ Scope (\_SB)
+ {
+ Method (_OSC, 4, NotSerialized)
+ {
+ /* Platform-Wide OSPM Capabilities */
+ If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
+ {
+ /* APEI support unconditionally */
+ Return (Arg3)
+ } Else {
+ CreateDWordField (Arg3, Zero, CDW1)
+ /* Set invalid UUID error bit */
+ Or (CDW1, 0x04, CDW1)
+ Return (Arg3)
+ }
+ }
+
+ //
+ // One Emulated aarch64 CPU with 1 core
+ //
+ Device(CPU0) { // Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ }
+ // Cadence UART
+ Device(COM0) {
+ Name(_HID, "CDNS0001")
+ Name(_UID, 0)
+ Name(_CRS, ResourceTemplate() {
+ Memory32Fixed(ReadWrite, FixedPcdGet64 (PcdCspSerialBase), FixedPcdGet32 (PcdCspSerialSize))
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x20 }
+ })
+ }
+
+ //Legacy IRQs
+ Device (LNKA)
+ {
+ Name (_HID, Eisaid ("PNP0C0F"))
+ Name (_UID, 1)
+ Name(_PRS, ResourceTemplate(){
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
+ })
+ Method(_DIS) {}
+ Method(_CRS) { Return (_PRS) }
+ Method(_SRS, 1) {}
+ }
+ Device (LNKB)
+ {
+ Name (_HID, Eisaid ("PNP0C0F"))
+ Name (_UID, 1)
+ Name(_PRS, ResourceTemplate(){
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
+ })
+ Method(_DIS) {}
+ Method(_CRS) { Return (_PRS) }
+ Method(_SRS, 1) {}
+ }
+ Device (LNKC)
+ {
+ Name (_HID, Eisaid ("PNP0C0F"))
+ Name (_UID, 1)
+ Name(_PRS, ResourceTemplate(){
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
+ })
+ Method(_DIS) {}
+ Method(_CRS) { Return (_PRS) }
+ Method(_SRS, 1) {}
+ }
+ Device (LNKD)
+ {
+ Name (_HID, Eisaid ("PNP0C0F"))
+ Name (_UID, 1)
+ Name(_PRS, ResourceTemplate(){
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
+ })
+ Method(_DIS) {}
+ Method(_CRS) { Return (_PRS) }
+ Method(_SRS, 1) {}
+ }
+
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08")) // _HID: Hardware ID
+ Name (_CID, EisaId ("PNP0A03")) // _CID: Compatible ID
+ Name (_SEG, 0x00) // _SEG: PCI Segment
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number
+ Name(_ADR,Zero)
+ NAME(_CCA,0) // Cache Coherent Architecture = FALSE
+
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+ Method (_OSC, 4, Serialized) // _OSC: Operating System Capabilities
+ {
+ Store (Arg3, Local0)
+ CreateDWordField (Local0, Zero, CDW1)
+ CreateDWordField (Local0, 0x04, CDW2)
+ CreateDWordField (Local0, 0x08, CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return (Local0)
+ }
+
+
+ Name (_UID, Zero) // _UID: Unique ID
+ Device (RP01)
+ {
+ Name (_ADR, 0x001C0000) // _ADR: Address
+ OperationRegion (PXCS, PCI_Config, Zero, 0x0380)
+ Field (PXCS, AnyAcc, NoLock, Preserve)
+ {
+ VDID, 32,
+ Offset (0x19),
+ SCBN, 8,
+ Offset (0x50),
+ L0SE, 1,
+ , 3,
+ LDIS, 1,
+ Offset (0x51),
+ Offset (0x52),
+ , 13,
+ LASX, 1,
+ Offset (0x54),
+ , 6,
+ HPCE, 1,
+ Offset (0x5A),
+ ABPX, 1,
+ , 2,
+ PDCX, 1,
+ , 2,
+ PDSX, 1,
+ Offset (0x5B),
+ Offset (0x60),
+ Offset (0x62),
+ PSPX, 1,
+ PMEP, 1,
+ Offset (0xA4),
+ D3HT, 2,
+ Offset (0xD8),
+ , 30,
+ HPEX, 1,
+ PMEX, 1,
+ Offset (0xE2),
+ , 2,
+ L23E, 1,
+ L23R, 1,
+ Offset (0x324),
+ , 3,
+ LEDM, 1
+ }
+
+ Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
+ {
+ Offset (0xDC),
+ , 30,
+ HPSX, 1,
+ PMSX, 1
+ }
+
+ Method (_STA, 0, NotSerialized) // _STA: Status
+ {
+ Return (0x0F)
+ }
+
+ Name (LTRV, Package (0x04)
+ {
+ Zero,
+ Zero,
+ Zero,
+ Zero
+ })
+
+ Name (OPTS, Zero)
+
+ Name (RPAV, Zero)
+
+ Method (_REG, 2, NotSerialized) // _REG: Region Availability
+ {
+ If (LAnd (LEqual (Arg0, 0x02), LEqual (Arg1, One)))
+ {
+ Store (One, RPAV)
+ }
+ }
+
+ Method (HPME, 0, Serialized)
+ {
+ If (LOr (PSPX, PMEP))
+ {
+ Store (PMEX, Local1)
+ Store (Zero, PMEX)
+ Sleep (0x32)
+ Store (One, PSPX)
+ Sleep (0x32)
+ If (PSPX)
+ {
+ Store (One, PSPX)
+ Sleep (0x32)
+ }
+ Store (Local1, PMEX)
+ }
+ If (PMSX)
+ {
+ Store (0xC8, Local0)
+ While (Local0)
+ {
+ Store (One, PMSX)
+ If (PMSX)
+ {
+ Decrement (Local0)
+ }
+ Else
+ {
+ Store (Zero, Local0)
+ }
+ }
+ }
+ }
+ }
+ Name(_PRT, Package()
+ {
+ Package(){0x0000ffff, 0, LNKA, 0}, // Slot 1, INTA
+ Package(){0x0000ffff, 1, LNKB, 0}, // Slot 1, INTB
+ Package(){0x0000ffff, 2, LNKC, 0}, // Slot 1, INTC
+ Package(){0x0000ffff, 3, LNKD, 0}, // Slot 1, INTD
+ })
+ Method (_CRS, 0, Serialized)
+ {
+ Name (PRT0, ResourceTemplate ()
+ {
+ /* bus number is from 0 - 1f */
+ WordBusNumber (ResourceConsumer, MinFixed, MaxFixed, SubDecode,
+ 0x0000,
+ 0x0000,
+ 0x001f,
+ 0x0000,
+ 0x0020)
+ DWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000,
+ 0x42000000,
+ 0x42FFFFFF,
+ 0x00000000,
+ 0x01000000)
+ DWordIO (ResourceConsumer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000,
+ 0x43000000,
+ 0x43FFFFFF,
+ 0x00000000,
+ 0x01000000)
+ })
+ Return (PRT0)
+ }
+ }
+ }
+}
diff --git a/CadencePkg/AcpiTables/Fadt.aslc b/CadencePkg/AcpiTables/Fadt.aslc
new file mode 100644
index 0000000..2035884
--- /dev/null
+++ b/CadencePkg/AcpiTables/Fadt.aslc
@@ -0,0 +1,87 @@
+/** @file
+* Fixed ACPI Description Table (FADT)
+*
+* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "CspPlatform.h"
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+ ),
+ 0, // UINT32 FirmwareCtrl
+ 0, // UINT32 Dsdt
+ EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
+ EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
+ 0, // UINT16 SciInt
+ 0, // UINT32 SmiCmd
+ 0, // UINT8 AcpiEnable
+ 0, // UINT8 AcpiDisable
+ 0, // UINT8 S4BiosReq
+ 0, // UINT8 PstateCnt
+ 0, // UINT32 Pm1aEvtBlk
+ 0, // UINT32 Pm1bEvtBlk
+ 0, // UINT32 Pm1aCntBlk
+ 0, // UINT32 Pm1bCntBlk
+ 0, // UINT32 Pm2CntBlk
+ 0, // UINT32 PmTmrBlk
+ 0, // UINT32 Gpe0Blk
+ 0, // UINT32 Gpe1Blk
+ 0, // UINT8 Pm1EvtLen
+ 0, // UINT8 Pm1CntLen
+ 0, // UINT8 Pm2CntLen
+ 0, // UINT8 PmTmrLen
+ 0, // UINT8 Gpe0BlkLen
+ 0, // UINT8 Gpe1BlkLen
+ 0, // UINT8 Gpe1Base
+ 0, // UINT8 CstCnt
+ 0, // UINT16 PLvl2Lat
+ 0, // UINT16 PLvl3Lat
+ 0, // UINT16 FlushSize
+ 0, // UINT16 FlushStride
+ 0, // UINT8 DutyOffset
+ 0, // UINT8 DutyWidth
+ 0, // UINT8 DayAlrm
+ 0, // UINT8 MonAlrm
+ 0, // UINT8 Century
+ 0, // UINT16 IaPcBootArch
+ 0, // UINT8 Reserved1
+ EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
+ 0, // UINT8 ResetValue
+ 0, //EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
+ EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
+ 0, // UINT64 XFirmwareCtrl
+ 0, // UINT64 XDsdt
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
+ NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
+ NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/CadencePkg/AcpiTables/Gtdt.aslc b/CadencePkg/AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000..ddc88d6
--- /dev/null
+++ b/CadencePkg/AcpiTables/Gtdt.aslc
@@ -0,0 +1,80 @@
+/** @file
+* Generic Timer Description Table (GTDT)
+*
+* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "CspPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
+#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL 0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+ #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+ #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED 0
+#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH 0
+
+#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
+ EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock;
+ EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[0];
+ EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[0];
+ } GENERIC_TIMER_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+ GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
+ {
+ ARM_ACPI_HEADER(
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ GENERIC_TIMER_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+ ),
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
+ 0, // UINT32 Reserved
+ FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
+ FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
+ FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
+ GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
+ SYSTEM_TIMER_BASE_ADDRESS, // UINT64 CntReadBasePhysicalAddress
+ 0, // UINT32 PlatformTimerCount
+ sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+ }
+ };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/CadencePkg/AcpiTables/Madt.aslc b/CadencePkg/AcpiTables/Madt.aslc
new file mode 100644
index 0000000..41a8eb9
--- /dev/null
+++ b/CadencePkg/AcpiTables/Madt.aslc
@@ -0,0 +1,71 @@
+/** @file
+* Multiple APIC Description Table (MADT)
+*
+* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
+* Copyright (c) 2016 Linaro Ltd. All rights reserved.
+* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include "CspPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi61.h>
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[1];
+ EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_1_GICR_STRUCTURE Gicr;
+} CSP_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+CSP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+ {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ CSP_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ ),
+ //
+ // MADT specific fields
+ //
+ 0, // LocalApicAddress
+ 0, // Flags
+ },
+ {
+ EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
+ 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, 0,
+ 0, 0, 0x19, 0, 0),
+ },
+ EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3),
+ /* GIC Redistributor */
+ {
+ EFI_ACPI_6_1_GICR, // UINT8 Type
+ sizeof(EFI_ACPI_6_1_GICR_STRUCTURE), // UINT8 Length
+ EFI_ACPI_RESERVED_WORD, // UINT16 Reserved
+ FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress
+ 0x00200000, // UINT32 DiscoveryRangeLength
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/CadencePkg/AcpiTables/Mcfg.aslc b/CadencePkg/AcpiTables/Mcfg.aslc
new file mode 100644
index 0000000..9fa03ca
--- /dev/null
+++ b/CadencePkg/AcpiTables/Mcfg.aslc
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ * Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ * Yi Li - yi.li@linaro.org
+*/
+#include "CspPlatform.h"
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define ACPI_5_0_MCFG_VERSION 0x1
+
+#pragma pack(1)
+typedef struct
+{
+ UINT64 BaseAddress;
+ UINT16 SegGroupNum;
+ UINT8 StartBusNum;
+ UINT8 EndBusNum;
+ UINT32 Reserved2;
+}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ UINT64 Reserved1;
+}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+ EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+ EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[2];
+}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+ {
+ {
+ EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+ ACPI_5_0_MCFG_VERSION,
+ 0x00, // Checksum will be updated at runtime
+ {EFI_ACPI_CSP_OEM_ID},
+ EFI_ACPI_CSP_OEM_TABLE_ID,
+ EFI_ACPI_CSP_OEM_REVISION,
+ EFI_ACPI_CSP_CREATOR_ID,
+ EFI_ACPI_CSP_CREATOR_REVISION
+ },
+ 0x0000000000000000, //Reserved
+ },
+ {
+
+ {
+ 0x0000000040000000, //Base Address
+ 0x0000, //Segment Group Number
+ 0x0, //Start Bus Number
+ 0x1f, //End Bus Number
+ 0x00000000, //Reserved
+ },
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
--
2.2.2
^ permalink raw reply related [flat|nested] 16+ messages in thread* Re: [staging/cadence-aarch64 PATCH v3 5/6] CadencePkg: Add ACPI tables for Cadence CSP platform.
2017-06-22 9:32 ` [staging/cadence-aarch64 PATCH v3 5/6] CadencePkg: Add ACPI tables " Scott Telford
@ 2017-06-29 16:17 ` Leif Lindholm
0 siblings, 0 replies; 16+ messages in thread
From: Leif Lindholm @ 2017-06-29 16:17 UTC (permalink / raw)
To: Scott Telford
Cc: edk2-devel, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
On Thu, Jun 22, 2017 at 10:32:00AM +0100, Scott Telford wrote:
> Add ACPI tables for Cadence CSP platform configured with a single
> Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root Complex.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Scott Telford <stelford@cadence.com>
Graeme also told me on the side that he is happy with this version of
the patch (but managed to delete it from his inbox), so:
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
> ---
> CadencePkg/AcpiTables/AcpiTables.inf | 50 ++++++
> CadencePkg/AcpiTables/CspPlatform.h | 46 ++++++
> CadencePkg/AcpiTables/Dsdt.asl | 307 +++++++++++++++++++++++++++++++++++
> CadencePkg/AcpiTables/Fadt.aslc | 87 ++++++++++
> CadencePkg/AcpiTables/Gtdt.aslc | 80 +++++++++
> CadencePkg/AcpiTables/Madt.aslc | 71 ++++++++
> CadencePkg/AcpiTables/Mcfg.aslc | 76 +++++++++
> 7 files changed, 717 insertions(+)
> create mode 100644 CadencePkg/AcpiTables/AcpiTables.inf
> create mode 100644 CadencePkg/AcpiTables/CspPlatform.h
> create mode 100644 CadencePkg/AcpiTables/Dsdt.asl
> create mode 100644 CadencePkg/AcpiTables/Fadt.aslc
> create mode 100644 CadencePkg/AcpiTables/Gtdt.aslc
> create mode 100644 CadencePkg/AcpiTables/Madt.aslc
> create mode 100644 CadencePkg/AcpiTables/Mcfg.aslc
>
> diff --git a/CadencePkg/AcpiTables/AcpiTables.inf b/CadencePkg/AcpiTables/AcpiTables.inf
> new file mode 100644
> index 0000000..4f79485
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/AcpiTables.inf
> @@ -0,0 +1,50 @@
> +## @file
> +#
> +# ACPI table data and ASL sources required to boot the platform.
> +#
> +# Copyright (c) 2014-2016, ARM Ltd. All rights reserved.
> +# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +#
> +# This program and the accompanying materials
> +# are licensed and made available under the terms and conditions of the BSD License
> +# which accompanies this distribution. The full text of the license may be found at
> +# http://opensource.org/licenses/bsd-license.php
> +#
> +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +#
> +##
> +
> +[Defines]
> + INF_VERSION = 0x00010005
> + BASE_NAME = CspAcpiTables
> + FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
> + MODULE_TYPE = USER_DEFINED
> + VERSION_STRING = 1.0
> +
> +[Sources]
> + Dsdt.asl
> + Fadt.aslc
> + Gtdt.aslc
> + Madt.aslc
> + Mcfg.aslc
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + ArmPlatformPkg/ArmPlatformPkg.dec
> + CadencePkg/CadenceCspPkg.dec
> + EmbeddedPkg/EmbeddedPkg.dec
> + MdePkg/MdePkg.dec
> + MdeModulePkg/MdeModulePkg.dec
> +
> +
> +[FixedPcd]
> + gArmTokenSpaceGuid.PcdGicDistributorBase
> + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
> + gArmTokenSpaceGuid.PcdGicRedistributorsBase
> + gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
> + gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
> + gCadenceCspTokenSpaceGuid.PcdCspSerialBase
> + gCadenceCspTokenSpaceGuid.PcdCspSerialSize
> diff --git a/CadencePkg/AcpiTables/CspPlatform.h b/CadencePkg/AcpiTables/CspPlatform.h
> new file mode 100644
> index 0000000..d3afe9e
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/CspPlatform.h
> @@ -0,0 +1,46 @@
> +/** @file
> +*
> +* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
> +* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2015, Linaro Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +*
> +**/
> +
> +
> +#ifndef _CSP_PLATFORM_H_
> +#define _CSP_PLATFORM_H_
> +
> +//
> +// ACPI table information used to initialize tables.
> +//
> +#define EFI_ACPI_CSP_OEM_ID 'C','D','N','S',' ',' ' // OEMID 6 bytes long
> +#define EFI_ACPI_CSP_OEM_TABLE_ID SIGNATURE_64('C','S','P',' ',' ',' ',' ',' ') // OEM table id 8 bytes long
> +#define EFI_ACPI_CSP_OEM_REVISION 0x00000002
> +#define EFI_ACPI_CSP_CREATOR_ID SIGNATURE_32('C','D','N','S')
> +#define EFI_ACPI_CSP_CREATOR_REVISION 0x00000001
> +
> +// A macro to initialise the common header part of EFI ACPI tables as defined by
> +// EFI_ACPI_DESCRIPTION_HEADER structure.
> +#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
> + Signature, /* UINT32 Signature */ \
> + sizeof (Type), /* UINT32 Length */ \
> + Revision, /* UINT8 Revision */ \
> + 0, /* UINT8 Checksum */ \
> + { EFI_ACPI_CSP_OEM_ID }, /* UINT8 OemId[6] */ \
> + EFI_ACPI_CSP_OEM_TABLE_ID, /* UINT64 OemTableId */ \
> + EFI_ACPI_CSP_OEM_REVISION, /* UINT32 OemRevision */ \
> + EFI_ACPI_CSP_CREATOR_ID, /* UINT32 CreatorId */ \
> + EFI_ACPI_CSP_CREATOR_REVISION /* UINT32 CreatorRevision */ \
> + }
> +
> +#endif
> diff --git a/CadencePkg/AcpiTables/Dsdt.asl b/CadencePkg/AcpiTables/Dsdt.asl
> new file mode 100644
> index 0000000..268777d
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Dsdt.asl
> @@ -0,0 +1,307 @@
> +/*
> +* Copyright (c) 2013, Al Stone <al.stone@linaro.org>
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +* All rights reserved.
> +*
> +* Redistribution and use in source and binary forms, with or without
> +* modification, are permitted provided that the following conditions
> +* are met:
> +*
> +* 1. Redistributions of source code must retain the above copyright
> +* notice, this list of conditions and the following disclaimer.
> +*
> +* 2. Redistributions in binary form must reproduce the above copyright
> +* notice, this list of conditions and the following disclaimer in the
> +* documentation and/or other materials provided with the distribution.
> +*
> +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
> +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
> +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
> +* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
> +* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
> +* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
> +* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
> +* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
> +* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
> +* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> +* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> +*
> +*
> +* NB: This License is also known as the "BSD 2-Clause License".
> +*
> +*
> +*
> +*/
> +
> +DefinitionBlock (
> + "dsdt.aml", // output filename
> + "DSDT", // table signature
> + 2, // DSDT compliance revision
> + "CDNS", // OEM ID
> + "CDNSCSP0", // table ID
> + 0x00000001) // OEM revision
> +{
> + Scope (\_SB)
> + {
> + Method (_OSC, 4, NotSerialized)
> + {
> + /* Platform-Wide OSPM Capabilities */
> + If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
> + {
> + /* APEI support unconditionally */
> + Return (Arg3)
> + } Else {
> + CreateDWordField (Arg3, Zero, CDW1)
> + /* Set invalid UUID error bit */
> + Or (CDW1, 0x04, CDW1)
> + Return (Arg3)
> + }
> + }
> +
> + //
> + // One Emulated aarch64 CPU with 1 core
> + //
> + Device(CPU0) { // Cluster 0, Cpu 0
> + Name(_HID, "ACPI0007")
> + Name(_UID, 0)
> + }
> + // Cadence UART
> + Device(COM0) {
> + Name(_HID, "CDNS0001")
> + Name(_UID, 0)
> + Name(_CRS, ResourceTemplate() {
> + Memory32Fixed(ReadWrite, FixedPcdGet64 (PcdCspSerialBase), FixedPcdGet32 (PcdCspSerialSize))
> + Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x20 }
> + })
> + }
> +
> + //Legacy IRQs
> + Device (LNKA)
> + {
> + Name (_HID, Eisaid ("PNP0C0F"))
> + Name (_UID, 1)
> + Name(_PRS, ResourceTemplate(){
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
> + })
> + Method(_DIS) {}
> + Method(_CRS) { Return (_PRS) }
> + Method(_SRS, 1) {}
> + }
> + Device (LNKB)
> + {
> + Name (_HID, Eisaid ("PNP0C0F"))
> + Name (_UID, 1)
> + Name(_PRS, ResourceTemplate(){
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
> + })
> + Method(_DIS) {}
> + Method(_CRS) { Return (_PRS) }
> + Method(_SRS, 1) {}
> + }
> + Device (LNKC)
> + {
> + Name (_HID, Eisaid ("PNP0C0F"))
> + Name (_UID, 1)
> + Name(_PRS, ResourceTemplate(){
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
> + })
> + Method(_DIS) {}
> + Method(_CRS) { Return (_PRS) }
> + Method(_SRS, 1) {}
> + }
> + Device (LNKD)
> + {
> + Name (_HID, Eisaid ("PNP0C0F"))
> + Name (_UID, 1)
> + Name(_PRS, ResourceTemplate(){
> + Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive, , ,) { 46 }
> + })
> + Method(_DIS) {}
> + Method(_CRS) { Return (_PRS) }
> + Method(_SRS, 1) {}
> + }
> +
> + Device (PCI0)
> + {
> + Name (_HID, EisaId ("PNP0A08")) // _HID: Hardware ID
> + Name (_CID, EisaId ("PNP0A03")) // _CID: Compatible ID
> + Name (_SEG, 0x00) // _SEG: PCI Segment
> + Name (_BBN, 0x00) // _BBN: BIOS Bus Number
> + Name(_ADR,Zero)
> + NAME(_CCA,0) // Cache Coherent Architecture = FALSE
> +
> + //
> + // OS Control Handoff
> + //
> + Name(SUPP, Zero) // PCI _OSC Support Field value
> + Name(CTRL, Zero) // PCI _OSC Control Field value
> + Method (_OSC, 4, Serialized) // _OSC: Operating System Capabilities
> + {
> + Store (Arg3, Local0)
> + CreateDWordField (Local0, Zero, CDW1)
> + CreateDWordField (Local0, 0x04, CDW2)
> + CreateDWordField (Local0, 0x08, CDW3)
> + // Save Capabilities DWord2 & 3
> + Store(CDW2,SUPP)
> + Store(CDW3,CTRL)
> + // Never allow SHPC (no SHPC controller in this system)
> + And(CTRL,0x1D,CTRL)
> + If(LNotEqual(Arg1,One)) { // Unknown revision
> + Or(CDW1,0x08,CDW1)
> + }
> + // Update DWORD3 in the buffer
> + Store(CTRL,CDW3)
> + Return (Local0)
> + }
> +
> +
> + Name (_UID, Zero) // _UID: Unique ID
> + Device (RP01)
> + {
> + Name (_ADR, 0x001C0000) // _ADR: Address
> + OperationRegion (PXCS, PCI_Config, Zero, 0x0380)
> + Field (PXCS, AnyAcc, NoLock, Preserve)
> + {
> + VDID, 32,
> + Offset (0x19),
> + SCBN, 8,
> + Offset (0x50),
> + L0SE, 1,
> + , 3,
> + LDIS, 1,
> + Offset (0x51),
> + Offset (0x52),
> + , 13,
> + LASX, 1,
> + Offset (0x54),
> + , 6,
> + HPCE, 1,
> + Offset (0x5A),
> + ABPX, 1,
> + , 2,
> + PDCX, 1,
> + , 2,
> + PDSX, 1,
> + Offset (0x5B),
> + Offset (0x60),
> + Offset (0x62),
> + PSPX, 1,
> + PMEP, 1,
> + Offset (0xA4),
> + D3HT, 2,
> + Offset (0xD8),
> + , 30,
> + HPEX, 1,
> + PMEX, 1,
> + Offset (0xE2),
> + , 2,
> + L23E, 1,
> + L23R, 1,
> + Offset (0x324),
> + , 3,
> + LEDM, 1
> + }
> +
> + Field (PXCS, AnyAcc, NoLock, WriteAsZeros)
> + {
> + Offset (0xDC),
> + , 30,
> + HPSX, 1,
> + PMSX, 1
> + }
> +
> + Method (_STA, 0, NotSerialized) // _STA: Status
> + {
> + Return (0x0F)
> + }
> +
> + Name (LTRV, Package (0x04)
> + {
> + Zero,
> + Zero,
> + Zero,
> + Zero
> + })
> +
> + Name (OPTS, Zero)
> +
> + Name (RPAV, Zero)
> +
> + Method (_REG, 2, NotSerialized) // _REG: Region Availability
> + {
> + If (LAnd (LEqual (Arg0, 0x02), LEqual (Arg1, One)))
> + {
> + Store (One, RPAV)
> + }
> + }
> +
> + Method (HPME, 0, Serialized)
> + {
> + If (LOr (PSPX, PMEP))
> + {
> + Store (PMEX, Local1)
> + Store (Zero, PMEX)
> + Sleep (0x32)
> + Store (One, PSPX)
> + Sleep (0x32)
> + If (PSPX)
> + {
> + Store (One, PSPX)
> + Sleep (0x32)
> + }
> + Store (Local1, PMEX)
> + }
> + If (PMSX)
> + {
> + Store (0xC8, Local0)
> + While (Local0)
> + {
> + Store (One, PMSX)
> + If (PMSX)
> + {
> + Decrement (Local0)
> + }
> + Else
> + {
> + Store (Zero, Local0)
> + }
> + }
> + }
> + }
> + }
> + Name(_PRT, Package()
> + {
> + Package(){0x0000ffff, 0, LNKA, 0}, // Slot 1, INTA
> + Package(){0x0000ffff, 1, LNKB, 0}, // Slot 1, INTB
> + Package(){0x0000ffff, 2, LNKC, 0}, // Slot 1, INTC
> + Package(){0x0000ffff, 3, LNKD, 0}, // Slot 1, INTD
> + })
> + Method (_CRS, 0, Serialized)
> + {
> + Name (PRT0, ResourceTemplate ()
> + {
> + /* bus number is from 0 - 1f */
> + WordBusNumber (ResourceConsumer, MinFixed, MaxFixed, SubDecode,
> + 0x0000,
> + 0x0000,
> + 0x001f,
> + 0x0000,
> + 0x0020)
> + DWordMemory (ResourceConsumer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
> + 0x00000000,
> + 0x42000000,
> + 0x42FFFFFF,
> + 0x00000000,
> + 0x01000000)
> + DWordIO (ResourceConsumer, MinFixed, MaxFixed, PosDecode, EntireRange,
> + 0x00000000,
> + 0x43000000,
> + 0x43FFFFFF,
> + 0x00000000,
> + 0x01000000)
> + })
> + Return (PRT0)
> + }
> + }
> + }
> +}
> diff --git a/CadencePkg/AcpiTables/Fadt.aslc b/CadencePkg/AcpiTables/Fadt.aslc
> new file mode 100644
> index 0000000..2035884
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Fadt.aslc
> @@ -0,0 +1,87 @@
> +/** @file
> +* Fixed ACPI Description Table (FADT)
> +*
> +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include "CspPlatform.h"
> +#include <Library/AcpiLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
> + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
> + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
> + ),
> + 0, // UINT32 FirmwareCtrl
> + 0, // UINT32 Dsdt
> + EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
> + EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
> + 0, // UINT16 SciInt
> + 0, // UINT32 SmiCmd
> + 0, // UINT8 AcpiEnable
> + 0, // UINT8 AcpiDisable
> + 0, // UINT8 S4BiosReq
> + 0, // UINT8 PstateCnt
> + 0, // UINT32 Pm1aEvtBlk
> + 0, // UINT32 Pm1bEvtBlk
> + 0, // UINT32 Pm1aCntBlk
> + 0, // UINT32 Pm1bCntBlk
> + 0, // UINT32 Pm2CntBlk
> + 0, // UINT32 PmTmrBlk
> + 0, // UINT32 Gpe0Blk
> + 0, // UINT32 Gpe1Blk
> + 0, // UINT8 Pm1EvtLen
> + 0, // UINT8 Pm1CntLen
> + 0, // UINT8 Pm2CntLen
> + 0, // UINT8 PmTmrLen
> + 0, // UINT8 Gpe0BlkLen
> + 0, // UINT8 Gpe1BlkLen
> + 0, // UINT8 Gpe1Base
> + 0, // UINT8 CstCnt
> + 0, // UINT16 PLvl2Lat
> + 0, // UINT16 PLvl3Lat
> + 0, // UINT16 FlushSize
> + 0, // UINT16 FlushStride
> + 0, // UINT8 DutyOffset
> + 0, // UINT8 DutyWidth
> + 0, // UINT8 DayAlrm
> + 0, // UINT8 MonAlrm
> + 0, // UINT8 Century
> + 0, // UINT16 IaPcBootArch
> + 0, // UINT8 Reserved1
> + EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
> + 0, // UINT8 ResetValue
> + 0, //EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
> + EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
> + 0, // UINT64 XFirmwareCtrl
> + 0, // UINT64 XDsdt
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
> + NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
> + NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Fadt;
> diff --git a/CadencePkg/AcpiTables/Gtdt.aslc b/CadencePkg/AcpiTables/Gtdt.aslc
> new file mode 100644
> index 0000000..ddc88d6
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Gtdt.aslc
> @@ -0,0 +1,80 @@
> +/** @file
> +* Generic Timer Description Table (GTDT)
> +*
> +* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include "CspPlatform.h"
> +#include <Library/AcpiLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#define GTDT_GLOBAL_FLAGS_MAPPED EFI_ACPI_6_1_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
> +#define GTDT_GLOBAL_FLAGS_NOT_MAPPED 0
> +#define GTDT_GLOBAL_FLAGS_EDGE EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
> +#define GTDT_GLOBAL_FLAGS_LEVEL 0
> +
> +// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
> +#ifdef SYSTEM_TIMER_BASE_ADDRESS
> + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
> +#else
> + #define GTDT_GLOBAL_FLAGS (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
> + #define SYSTEM_TIMER_BASE_ADDRESS 0xFFFFFFFFFFFFFFFF
> +#endif
> +
> +#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
> +#define GTDT_TIMER_LEVEL_TRIGGERED 0
> +#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
> +#define GTDT_TIMER_ACTIVE_HIGH 0
> +
> +#define GTDT_GTIMER_FLAGS (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
> +
> +#pragma pack (1)
> +
> +typedef struct {
> + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
> + EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock;
> + EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[0];
> + EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[0];
> + } GENERIC_TIMER_DESCRIPTION_TABLE;
> +
> +#pragma pack ()
> +
> + GENERIC_TIMER_DESCRIPTION_TABLE Gtdt = {
> + {
> + ARM_ACPI_HEADER(
> + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
> + GENERIC_TIMER_DESCRIPTION_TABLE,
> + EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
> + ),
> + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
> + 0, // UINT32 Reserved
> + FixedPcdGet32 (PcdArmArchTimerSecIntrNum), // UINT32 SecurePL1TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
> + FixedPcdGet32 (PcdArmArchTimerIntrNum), // UINT32 NonSecurePL1TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
> + FixedPcdGet32 (PcdArmArchTimerVirtIntrNum), // UINT32 VirtualTimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
> + FixedPcdGet32 (PcdArmArchTimerHypIntrNum), // UINT32 NonSecurePL2TimerGSIV
> + GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
> + SYSTEM_TIMER_BASE_ADDRESS, // UINT64 CntReadBasePhysicalAddress
> + 0, // UINT32 PlatformTimerCount
> + sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
> + }
> + };
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Gtdt;
> diff --git a/CadencePkg/AcpiTables/Madt.aslc b/CadencePkg/AcpiTables/Madt.aslc
> new file mode 100644
> index 0000000..41a8eb9
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Madt.aslc
> @@ -0,0 +1,71 @@
> +/** @file
> +* Multiple APIC Description Table (MADT)
> +*
> +* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
> +* Copyright (c) 2016 Linaro Ltd. All rights reserved.
> +* Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +**/
> +
> +#include "CspPlatform.h"
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi61.h>
> +
> +//
> +// Multiple APIC Description Table
> +//
> +#pragma pack (1)
> +
> +typedef struct {
> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
> + EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[1];
> + EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
> + EFI_ACPI_6_1_GICR_STRUCTURE Gicr;
> +} CSP_MULTIPLE_APIC_DESCRIPTION_TABLE;
> +
> +#pragma pack ()
> +
> +CSP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
> + {
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
> + CSP_MULTIPLE_APIC_DESCRIPTION_TABLE,
> + EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
> + ),
> + //
> + // MADT specific fields
> + //
> + 0, // LocalApicAddress
> + 0, // Flags
> + },
> + {
> + EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
> + 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 23, 0,
> + 0, 0, 0x19, 0, 0),
> + },
> + EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3),
> + /* GIC Redistributor */
> + {
> + EFI_ACPI_6_1_GICR, // UINT8 Type
> + sizeof(EFI_ACPI_6_1_GICR_STRUCTURE), // UINT8 Length
> + EFI_ACPI_RESERVED_WORD, // UINT16 Reserved
> + FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress
> + 0x00200000, // UINT32 DiscoveryRangeLength
> + }
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Madt;
> diff --git a/CadencePkg/AcpiTables/Mcfg.aslc b/CadencePkg/AcpiTables/Mcfg.aslc
> new file mode 100644
> index 0000000..9fa03ca
> --- /dev/null
> +++ b/CadencePkg/AcpiTables/Mcfg.aslc
> @@ -0,0 +1,76 @@
> +/*
> + * Copyright (c) 2013 Linaro Limited
> + * Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
> + *
> + * All rights reserved. This program and the accompanying materials
> + * are made available under the terms of the BSD License which accompanies
> + * this distribution, and is available at
> + * http://opensource.org/licenses/bsd-license.php
> + *
> + * Contributors:
> + * Yi Li - yi.li@linaro.org
> +*/
> +#include "CspPlatform.h"
> +#include <Library/AcpiLib.h>
> +#include <Library/ArmLib.h>
> +#include <Library/PcdLib.h>
> +#include <IndustryStandard/Acpi.h>
> +
> +#define ACPI_5_0_MCFG_VERSION 0x1
> +
> +#pragma pack(1)
> +typedef struct
> +{
> + UINT64 BaseAddress;
> + UINT16 SegGroupNum;
> + UINT8 StartBusNum;
> + UINT8 EndBusNum;
> + UINT32 Reserved2;
> +}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
> +
> +typedef struct
> +{
> + EFI_ACPI_DESCRIPTION_HEADER Header;
> + UINT64 Reserved1;
> +}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
> +
> +typedef struct
> +{
> + EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
> + EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[2];
> +}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
> +#pragma pack()
> +
> +EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
> +{
> + {
> + {
> + EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
> + sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
> + ACPI_5_0_MCFG_VERSION,
> + 0x00, // Checksum will be updated at runtime
> + {EFI_ACPI_CSP_OEM_ID},
> + EFI_ACPI_CSP_OEM_TABLE_ID,
> + EFI_ACPI_CSP_OEM_REVISION,
> + EFI_ACPI_CSP_CREATOR_ID,
> + EFI_ACPI_CSP_CREATOR_REVISION
> + },
> + 0x0000000000000000, //Reserved
> + },
> + {
> +
> + {
> + 0x0000000040000000, //Base Address
> + 0x0000, //Segment Group Number
> + 0x0, //Start Bus Number
> + 0x1f, //End Bus Number
> + 0x00000000, //Reserved
> + },
> + }
> +};
> +
> +//
> +// Reference the table being generated to prevent the optimizer from removing the
> +// data structure from the executable
> +//
> +VOID* CONST ReferenceAcpiTable = &Mcfg;
> --
> 2.2.2
>
^ permalink raw reply [flat|nested] 16+ messages in thread
* [staging/cadence-aarch64 PATCH v3 6/6] CadencePkg: Add .dsc, .fdf and .dec files for Cadence CSP platform.
2017-06-22 9:31 [staging/cadence-aarch64 PATCH v3 0/6] CadencePkg: Add package for Cadence hardware IP support Scott Telford
` (4 preceding siblings ...)
2017-06-22 9:32 ` [staging/cadence-aarch64 PATCH v3 5/6] CadencePkg: Add ACPI tables " Scott Telford
@ 2017-06-22 9:32 ` Scott Telford
5 siblings, 0 replies; 16+ messages in thread
From: Scott Telford @ 2017-06-22 9:32 UTC (permalink / raw)
To: edk2-devel, leif.lindholm, ard.biesheuvel, graeme.gregory, afish,
michael.d.kinney
Add .dsc, .fdf and .dec files for a Cadence CSP platform configured
with a single Cortex-A53, GIC-500, Cadence UART and Cadence PCIe Root
Complex.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Scott Telford <stelford@cadence.com>
---
CadencePkg/CadenceCsp.dsc | 672 +++++++++++++++++++++++++++++++++++++++++++
CadencePkg/CadenceCsp.fdf | 412 ++++++++++++++++++++++++++
CadencePkg/CadenceCspPkg.dec | 55 ++++
3 files changed, 1139 insertions(+)
create mode 100644 CadencePkg/CadenceCsp.dsc
create mode 100644 CadencePkg/CadenceCsp.fdf
create mode 100644 CadencePkg/CadenceCspPkg.dec
diff --git a/CadencePkg/CadenceCsp.dsc b/CadencePkg/CadenceCsp.dsc
new file mode 100644
index 0000000..eb98a29
--- /dev/null
+++ b/CadencePkg/CadenceCsp.dsc
@@ -0,0 +1,672 @@
+#
+# Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = CadenceCsp
+ PLATFORM_GUID = 262f8c6b-047b-4afe-b317-7c90b795beb8
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 1.25
+!ifdef $(EDK2_OUT_DIR)
+ OUTPUT_DIRECTORY = $(EDK2_OUT_DIR)
+!else
+ OUTPUT_DIRECTORY = Build/CadenceCsp
+!endif
+ SUPPORTED_ARCHITECTURES = AARCH64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = CadencePkg/CadenceCsp.fdf
+
+ SECURE_BOOT_ENABLE = FALSE
+
+[LibraryClasses.common]
+ ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+ ArmPlatformLib|CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
+ ArmMmuLib|ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf
+ TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+ # Virtio Support
+ VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
+ VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+!endif
+
+!if $(TARGET) == RELEASE
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+!else
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+!endif
+ DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
+
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+
+ #
+ # Assume everything is fixed at build
+ #
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+
+ # Networking Requirements
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+ # ARM Architectural Libraries
+ CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLib.inf
+ CpuExceptionHandlerLib|ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf
+ ArmDisassemblerLib|ArmPkg/Library/ArmDisassemblerLib/ArmDisassemblerLib.inf
+ DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchLib/ArmGicArchLib.inf
+ ArmPlatformStackLib|ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf
+ ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf
+ ArmGenericTimerCounterLib|ArmPkg/Library/ArmGenericTimerPhyCounterLib/ArmGenericTimerPhyCounterLib.inf
+
+ PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf
+ EfiResetSystemLib|CadencePkg/Library/CadenceCspResetSystemLib/CadenceCspResetSystemLib.inf
+
+ RealTimeClockLib|EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf
+
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+ PlatformBdsLib|ArmPlatformPkg/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+ CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+ BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
+
+# CSP Libraries
+ SerialPortLib|CadencePkg/Library/CadenceCspSerialPortLib/CspSerialPortLib.inf
+
+ #
+ # Uncomment (and comment out the next line) For RealView Debugger. The Standard IO window
+ # in the debugger will show load and unload commands for symbols. You can cut and paste this
+ # into the command window to load symbols. We should be able to use a script to do this, but
+ # the version of RVD I have does not support scripts accessing system memory.
+ #
+ #PeCoffExtraActionLib|ArmPkg/Library/RvdPeCoffExtraActionLib/RvdPeCoffExtraActionLib.inf
+ PeCoffExtraActionLib|ArmPkg/Library/DebugPeCoffExtraActionLib/DebugPeCoffExtraActionLib.inf
+ #PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+ DebugAgentTimerLib|EmbeddedPkg/Library/DebugAgentTimerLibNull/DebugAgentTimerLibNull.inf
+
+ AcpiLib|EmbeddedPkg/Library/AcpiLib/AcpiLib.inf
+ FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
+
+ ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
+ FileHandleLib|MdePkg/Library/UefiFileHandleLib/UefiFileHandleLib.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+ #
+ # Secure Boot dependencies
+ #
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+ AuthVariableLib|SecurityPkg/Library/AuthVariableLib/AuthVariableLib.inf
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+
+ # re-use the UserPhysicalPresent() dummy implementation from the ovmf tree
+ PlatformSecureLib|OvmfPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
+!else
+ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurementLibNull.inf
+ AuthVariableLib|MdeModulePkg/Library/AuthVariableLibNull/AuthVariableLibNull.inf
+!endif
+ VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf
+
+[LibraryClasses.common.SEC]
+ ArmPlatformSecLib|CadencePkg/Library/CadenceCspSecLib/CadenceCspSecLib.inf
+ ArmPlatformLib|CadencePkg/Library/CadenceCspLib/CadenceCspLibSec.inf
+ DebugAgentLib|ArmPkg/Library/DebugAgentSymbolsBaseLib/DebugAgentSymbolsBaseLib.inf
+ DefaultExceptionHandlerLib|ArmPkg/Library/DefaultExceptionHandlerLib/DefaultExceptionHandlerLibBase.inf
+
+!ifdef $(EDK2_SKIP_PEICORE)
+ PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
+ ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf
+ LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf
+ HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf
+ PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+!endif
+
+ # Trustzone Support
+ ArmTrustedMonitorLib|ArmPlatformPkg/Library/ArmTrustedMonitorLibNull/ArmTrustedMonitorLibNull.inf
+
+ ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf
+
+
+[LibraryClasses.common.PEI_CORE]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.PEIM]
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+ PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf
+
+[LibraryClasses.common.SEC, LibraryClasses.common.PEIM]
+ MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf
+
+[LibraryClasses.common.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.common.DXE_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.UEFI_APPLICATION]
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER]
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+!endif
+
+[LibraryClasses.ARM, LibraryClasses.AARCH64]
+ #
+ # It is not possible to prevent the ARM compiler for generic intrinsic functions.
+ # This library provides the instrinsic functions generate by a given compiler.
+ # [LibraryClasses.ARM] and NULL mean link this library into all ARM images.
+ #
+ NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+
+ # Add support for GCC stack protector
+ NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf
+
+[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ PciHostBridgeLib|CadencePkg/Library/CadencePciHostBridgeLib/CdnsPciHostBridgeLib.inf
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+
+[BuildOptions]
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]
+ GCC:*_*_ARM_DLINK_FLAGS = -z common-page-size=0x1000
+ GCC:*_*_AARCH64_DLINK_FLAGS = -z common-page-size=0x10000
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+ gEfiMdePkgTokenSpaceGuid.PcdComponentNameDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnosticsDisable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdComponentName2Disable|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdDriverDiagnostics2Disable|TRUE
+
+ #
+ # Control what commands are supported from the UI
+ # Turn these on and off to add features or save size
+ #
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMacBoot|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDirCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHobCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedHwDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedPciDebugCmd|TRUE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedIoEnable|FALSE
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedScriptCmd|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdCacheEnable|TRUE
+
+ # Use the Vector Table location in CpuDxe. We will not copy the Vector Table at PcdCpuVectorBaseAddress
+ gArmTokenSpaceGuid.PcdRelocateVectorTable|FALSE
+
+ gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE
+
+[PcdsFixedAtBuild.common]
+ gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"Cadence CSP"
+!ifdef $(FIRMWARE_VER)
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+!endif
+
+ # Only one core enters UEFI, and PSCI is implemented in EL3 by ATF
+ gArmPlatformTokenSpaceGuid.PcdCoreCount|1
+ gArmTokenSpaceGuid.PcdVFPEnabled|1
+
+ # Stacks for MPCores in Normal World
+ # Non-Trusted SRAM
+ gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000
+ gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x0
+
+ # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+ gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000
+
+ #
+ # ARM Pcds
+ #
+ # Stacks for MPCores in Secure World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x3F000000
+ # Stacks for MPCores in Normal World
+ gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x3F020000
+
+ gArmTokenSpaceGuid.PcdSystemMemoryBase|0x10000000
+ gArmTokenSpaceGuid.PcdSystemMemorySize|0x30000000
+
+ ## Trustzone enable (to make the transition from EL3 to NS EL2 in ArmPlatformPkg/Sec)
+ gArmTokenSpaceGuid.PcdTrustzoneSupport|TRUE
+
+ #
+ # ARM General Interrupt Controller
+ #
+ gArmTokenSpaceGuid.PcdGicDistributorBase|0xfd100000
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xfd140000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE
+
+ #
+ # Cadence PCIe Root Complex
+ #
+ gArmTokenSpaceGuid.PcdPciBusMax|31
+ gArmTokenSpaceGuid.PcdPciIoBase|0x0
+ gArmTokenSpaceGuid.PcdPciIoSize|0x01000000
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x42000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x01000000
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000
+ gArmTokenSpaceGuid.PcdPciIoTranslation|0x43000000
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|24
+
+ # Use the serial console (ConIn & ConOut)
+ gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+ gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+ #
+ # ARM Architectural Timer Frequency
+ #
+ # Set tick frequency value to 100MHz
+ gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000
+
+ # the entire address space can be covered by 36 bit VAs
+ gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36
+
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|1000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
+ gEfiMdePkgTokenSpaceGuid.PcdDebugClearMemoryValue|0xAF
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|1
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+
+ # DEBUG_ASSERT_ENABLED 0x01
+ # DEBUG_PRINT_ENABLED 0x02
+ # DEBUG_CODE_ENABLED 0x04
+ # CLEAR_MEMORY_ENABLED 0x08
+ # ASSERT_BREAKPOINT_ENABLED 0x10
+ # ASSERT_DEADLOOP_ENABLED 0x20
+!if $(TARGET) == RELEASE
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x21
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2f
+!endif
+
+ # DEBUG_INIT 0x00000001 // Initialization
+ # DEBUG_WARN 0x00000002 // Warnings
+ # DEBUG_LOAD 0x00000004 // Load events
+ # DEBUG_FS 0x00000008 // EFI File system
+ # DEBUG_POOL 0x00000010 // Alloc & Free (pool)
+ # DEBUG_PAGE 0x00000020 // Alloc & Free (page)
+ # DEBUG_INFO 0x00000040 // Informational debug messages
+ # DEBUG_DISPATCH 0x00000080 // PEI/DXE/SMM Dispatchers
+ # DEBUG_VARIABLE 0x00000100 // Variable
+ # DEBUG_BM 0x00000400 // Boot Manager
+ # DEBUG_BLKIO 0x00001000 // BlkIo Driver
+ # DEBUG_NET 0x00004000 // SNP Driver
+ # DEBUG_UNDI 0x00010000 // UNDI Driver
+ # DEBUG_LOADFILE 0x00020000 // LoadFile
+ # DEBUG_EVENT 0x00080000 // Event messages
+ # DEBUG_GCD 0x00100000 // Global Coherency Database changes
+ # DEBUG_CACHE 0x00200000 // Memory range cachability changes
+ # DEBUG_VERBOSE 0x00400000 // Detailed debug messages that may
+ # // significantly impact boot performance
+ # DEBUG_ERROR 0x80000000 // Error
+# gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000000F
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000054F
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedAutomaticBootCommand|""
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
+ gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
+
+ #
+ # Optional feature to help prevent EFI memory map fragments
+ # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
+ # Values are in EFI Pages (4K). DXE Core will make sure that
+ # at least this much of each type of memory can be allocated
+ # from a single memory range. This way you only end up with
+ # maximum of two fragements for each type in the memory map
+ # (the memory used, and the free memory that was prereserved
+ # but not used).
+ #
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType|0
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|80
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|65
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode|400
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData|20000
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode|20
+ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData|0
+
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ # override the default values from SecurityPkg to ensure images from all sources are verified in secure boot
+ gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdFixedMediaImageVerificationPolicy|0x04
+ gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04
+!endif
+
+# Generic UART PCDs
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+#
+# Cadence CSP Base Components PCDs
+#
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegBase|0xfd020000
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegSize|0x00001000
+ gCadenceCspTokenSpaceGuid.PcdCspSerialBase|0xfd000000
+ gCadenceCspTokenSpaceGuid.PcdCspSerialSize|0x00001000
+
+# Cadence xHCI
+# gCadenceCspTokenSpaceGuid.PcdCadenceUsbXhciBaseAddress|0x70000000
+# gCadenceCspTokenSpaceGuid.PcdCadenceUsbXhciSize|0x7009ffff
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+ #
+ # SEC
+ #
+ CadencePkg/Sec/Sec.inf {
+ <LibraryClasses>
+ # Use the implementation which set the Secure bits
+ ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf
+ }
+
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
+ #
+ # SATA Controller
+ #
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
+
+ #
+ # NVMe boot devices
+ #
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+ #
+ # Networking stack
+ #
+ MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+ # FV Filesystem
+ MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ }
+
+!ifdef ARM_SBSA_ACS
+ # ARM SBSA ACS app
+ AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf {
+ <LibraryClasses>
+ SbsaPalLib|AppPkg/Applications/sbsa-acs/platform/pal_uefi/SbsaPalLib.inf
+ SbsaValLib|AppPkg/Applications/sbsa-acs/val/SbsaValLib.inf
+ ShellCEntryLib|ShellPkg/Library/UefiShellCEntryLib/UefiShellCEntryLib.inf
+ }
+!endif
+
+ #
+ # PEI Phase modules
+ #
+!ifdef EDK2_SKIP_PEICORE
+ # UEFI is placed in RAM by bootloader
+ ArmPlatformPkg/PrePi/PeiUniCore.inf {
+ <LibraryClasses>
+ ArmPlatformLib|CadencePkg/Library/CadenceCspLib/CadenceCspLib.inf
+ }
+!else
+ # UEFI lives in FLASH and copies itself to RAM
+ ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ MdeModulePkg/Core/Pei/PeiMain.inf
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+ ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ Nt32Pkg/BootModePei/BootModePei.inf
+ MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+!endif
+
+ #
+ # DXE
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
+
+ #
+ # Architectural Protocols
+ #
+ ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
+ <LibraryClasses>
+ NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
+ }
+ SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!else
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+!endif
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ #
+ # ACPI Support
+ #
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ CadencePkg/AcpiTables/AcpiTables.inf
+
+ ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+ # Required by PCI
+ UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+
+ #
+ # PCI Support
+ #
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+!ifdef INTEL_UNDI_BIN
+ CadencePkg/Drivers/IntelUndiPkg/Binary/GigUndiDxe.inf
+!endif
+
+ # Simple TextIn/TextOut for UEFI Terminal
+ EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+ # SMBIOS Support
+
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+ #
+ # Platform Driver
+ #
+ OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ FatPkg/EnhancedFatDxe/Fat.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ #
+ # Bds
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
diff --git a/CadencePkg/CadenceCsp.fdf b/CadencePkg/CadenceCsp.fdf
new file mode 100644
index 0000000..ecea87a
--- /dev/null
+++ b/CadencePkg/CadenceCsp.fdf
@@ -0,0 +1,412 @@
+#
+# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into the Flash Device Image. Each FD section
+# defines one flash "device" image. A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash" image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.Sec_CDNS_CSP_AARCH64_EFI]
+BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdSecureFdBaseAddress #The base address of the Secure FLASH Device.
+Size = 0x00020000|gArmTokenSpaceGuid.PcdSecureFdSize #The size in bytes of the Secure FLASH Device
+ErasePolarity = 1
+BlockSize = 0x00002000
+NumBlocks = 0x10
+
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00020000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FV = FVMAIN_SEC
+
+
+[FD.CDNS_CSP_AARCH64_EFI]
+BaseAddress = 0x0020000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
+Size = 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize = 0x00001000
+NumBlocks = 0x400
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00280000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FVMAIN_SEC]
+FvAlignment = 8
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+ INF CadencePkg/Sec/Sec.inf
+
+
+[FV.FvMain]
+BlockSize = 0x40
+NumBlocks = 0 # This FV gets compressed so make it just big enough
+FvAlignment = 16 # FV alignment and FV attributes setting.
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+FvNameGuid = b1e2a5cf-5357-4fc8-9532-49f3ce327bd3
+
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+ #
+ # PI DXE Drivers producing Architectural Protocols (EFI Services)
+ #
+ INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+!if $(SECURE_BOOT_ENABLE) == TRUE
+ INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
+!endif
+ INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+ INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+ INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+ # Required by PCI
+ INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+
+ #
+ # PCI Support
+ #
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+!ifdef INTEL_UNDI_BIN
+ INF CadencePkg/Drivers/IntelUndiPkg/Binary/GigUndiDxe.inf
+!endif
+
+ # ACPI Support
+ #
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ INF RuleOverride=ACPITABLE CadencePkg/AcpiTables/AcpiTables.inf
+
+ #
+ # Multiple Console IO support
+ #
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+
+ INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+ INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+ #
+ # FAT filesystem + GPT/MBR partitioning
+ #
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF FatBinPkg/EnhancedFatDxe/Fat.inf
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+ # SMBIOS Support
+ #
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+
+ #
+ # Platform Driver
+ #
+ INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
+ #
+ # SATA Controller
+ #
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf
+
+ #
+ # NVMe boot devices
+ #
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ #
+ # UEFI application (Shell Embedded Boot Loader)
+ #
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ #
+ # Networking stack
+ #
+ INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+ INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+ INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+ INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+ INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf
+ INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+ INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+ INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+ INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
+
+!ifdef ARM_SBSA_ACS
+ # ARM SBSA ACS app
+ INF AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf
+!endif
+
+ #
+ # Bds
+ #
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+ #
+ # TianoCore logo (splash screen)
+ #
+ FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {
+ SECTION RAW = MdeModulePkg/Logo/Logo.bmp
+ }
+
+ # FV Filesystem
+ INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
+
+ #
+ # FDT installation
+ #
+ # The UEFI driver is at the end of the list of the driver to be dispatched
+ # after the device drivers (eg: Ethernet) to ensure we have support for them.
+# INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf
+
+[FV.FVMAIN_COMPACT]
+FvAlignment = 16
+ERASE_POLARITY = 1
+MEMORY_MAPPED = TRUE
+STICKY_WRITE = TRUE
+LOCK_CAP = TRUE
+LOCK_STATUS = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP = TRUE
+WRITE_STATUS = TRUE
+WRITE_LOCK_CAP = TRUE
+WRITE_LOCK_STATUS = TRUE
+READ_DISABLED_CAP = TRUE
+READ_ENABLED_CAP = TRUE
+READ_STATUS = TRUE
+READ_LOCK_CAP = TRUE
+READ_LOCK_STATUS = TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+ INF ArmPlatformPkg/PrePi/PeiUniCore.inf
+!else
+ INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+ INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+ INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+!endif
+
+ FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FVMAIN
+ }
+ }
+
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+
+############################################################################
+# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #
+############################################################################
+#
+#[Rule.Common.DXE_DRIVER]
+# FILE DRIVER = $(NAMED_GUID) {
+# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+# COMPRESS PI_STD {
+# GUIDED {
+# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+# UI STRING="$(MODULE_NAME)" Optional
+# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+# }
+# }
+# }
+#
+############################################################################
+
+[Rule.Common.SEC]
+ FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.PEI_CORE]
+ FILE PEI_CORE = $(NAMED_GUID) FIXED {
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING ="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM]
+ FILE PEIM = $(NAMED_GUID) FIXED {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.PEIM.TIANOCOMPRESSED]
+ FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {
+ PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ GUIDED 4caac18f-ffe5-48f2-86a5-23a615120637 PROCESSING_REQUIRED = TRUE {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+ }
+
+[Rule.Common.DXE_CORE]
+ FILE DXE_CORE = $(NAMED_GUID) {
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ UI STRING="$(MODULE_NAME)" Optional
+ }
+
+[Rule.Common.UEFI_APPLICATION]
+ FILE APPLICATION = $(NAMED_GUID) {
+ UI STRING ="$(MODULE_NAME)" Optional
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ }
+
+[Rule.Common.UEFI_DRIVER.BINARY]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional |.depex
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.UEFI_APPLICATION.BINARY]
+ FILE APPLICATION = $(NAMED_GUID) {
+ PE32 PE32 |.efi
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI |.acpi
+ RAW ASL |.aml
+ }
diff --git a/CadencePkg/CadenceCspPkg.dec b/CadencePkg/CadenceCspPkg.dec
new file mode 100644
index 0000000..c5776cf
--- /dev/null
+++ b/CadencePkg/CadenceCspPkg.dec
@@ -0,0 +1,55 @@
+#/** @file
+# Cadence CSP package.
+#
+# Copyright (c) 2012-2015, ARM Limited. All rights reserved.
+# Copyright (c) 2017, Cadence Design Systems, Inc. All rights reserved.
+#
+# This program and the accompanying materials are licensed and made available
+# under the terms and conditions of the BSD License which accompanies this
+# distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ DEC_SPECIFICATION = 1.25
+ PACKAGE_NAME = CadenceCspPkg
+ PACKAGE_GUID = 593f66c2-fb57-4aa7-8bd0-149d52443f21
+ PACKAGE_VERSION = 0.1
+
+################################################################################
+#
+# Include Section - list of Include Paths that are provided by this package.
+# Comments are used for Keywords and Module Types.
+#
+# Supported Module Types:
+# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION
+#
+################################################################################
+[Includes.common]
+ Include # Root include for the package
+
+[Guids.common]
+ gCadenceCspTokenSpaceGuid = { 0x593f66c2, 0xfb57, 0x4aa7, { 0x8b, 0xd0, 0x14, 0x9d, 0x52, 0x44, 0x3f, 0x21 } }
+
+[PcdsFixedAtBuild.common]
+ # Cadence CSP System Registers
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegBase|0|UINT64|0x000000C0
+ gCadenceCspTokenSpaceGuid.PcdCspSysRegSize|0|UINT32|0x000000D0
+
+ # Cadence UART
+ gCadenceCspTokenSpaceGuid.PcdCspSerialBase|0|UINT64|0x000000C1
+ gCadenceCspTokenSpaceGuid.PcdCspSerialSize|0|UINT32|0x000000D1
+
+ # Cadence PCIe
+ gCadenceCspTokenSpaceGuid.PcdPcieRootPortBaseAddress|0xfb000000|UINT64|0x0000000C
+ gCadenceCspTokenSpaceGuid.PcdPcie1RootPortBaseAddress|0xfc000000|UINT64|0x000000CD
+ gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceBaseAddress|0x40000000|UINT64|0x00000011
+ gCadenceCspTokenSpaceGuid.PcdPciConfigurationSpaceSize|0x02000000|UINT64|0x00000012
+
+ ## Timeout value for displaying progressing bar in before boot OS.
+ # According to UEFI 2.0 spec, the default TimeOut should be 0xffff.
+ gArmPlatformTokenSpaceGuid.PcdPlatformBootTimeOut|3|UINT16|0x0000001A
--
2.2.2
^ permalink raw reply related [flat|nested] 16+ messages in thread