From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-x22e.google.com (mail-wr0-x22e.google.com [IPv6:2a00:1450:400c:c0c::22e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1A2CF21CB57B8 for ; Fri, 30 Jun 2017 04:00:09 -0700 (PDT) Received: by mail-wr0-x22e.google.com with SMTP id r103so202603228wrb.0 for ; Fri, 30 Jun 2017 04:01:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=ISR+Cre/tP0uWNNV+D7AKPjvw3RDj7+efTkdFZc8HqA=; b=Xeug1gbFOscLYIgUx3YGKksOKD/JAjZH3Uj/T5OLbMUXuLCZxZ/44jtqBwgu1oFw37 uuv2GJX/PTEAZ8Is51EWSBMof6EMBHtTT+pMhkbbIduSYoEPsuoVv3cgTU/+Ys9FRuJA Bf+pLrvfJ6dBrTZYUUnQoqw5ePBwDC43bU8/U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ISR+Cre/tP0uWNNV+D7AKPjvw3RDj7+efTkdFZc8HqA=; b=U1uTjvCk3TIOFYtUNfovXZmVJGw9AXQFEvI3vPpwscXOhzzIEzIAhOd6jKHGyBQ+X/ KBKd+S/5eufPE2V8XL/bjqcfUMLETeowxh1rXhGDO3hSjgYcNBtYkJLD3kUgRvHVBzU+ v4UwDO5JdMil+A57FR939Yb3z9KicW3ycWtwt3pcD48vYQUEc2i0n4macXkJRyEp1gav CPjs0cEnbKFeHnyDSODcb1D4p+62u+KVQM3CLX2k1rRs8EfbRWThXImM0YPffTGXJFWa 8iAcEnQHXZeOQAZJiUOSPcQe2tV99UwEH89uh8fUHUhsg22lOLiydlQXH8HDmDCAqZh2 9Hhw== X-Gm-Message-State: AKS2vOwZmSMX2/P+Z8zbQ9r7tVSy8hVSO3ks8Xn/2v5Zapf9cqYo2/Cy 5y536SGJVNMIkTlw X-Received: by 10.223.163.92 with SMTP id d28mr26271706wrb.98.1498820501171; Fri, 30 Jun 2017 04:01:41 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id l8sm4095775wmd.15.2017.06.30.04.01.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Jun 2017 04:01:40 -0700 (PDT) Date: Fri, 30 Jun 2017 12:01:39 +0100 From: Leif Lindholm To: Jun Nie Cc: Ard Biesheuvel , edk2-devel@lists.01.org, linaro-uefi@lists.linaro.org, Alexei.Fedorov@arm.com, evan.lloyd@arm.com Message-ID: <20170630110139.GA26676@bivouac.eciton.net> References: MIME-Version: 1.0 In-Reply-To: User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: How to add support to different reg offset definition to share the same driver code? X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 30 Jun 2017 11:00:09 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Jun, I think there is more than one benefit in mimicing the Linux driver, so I would lean towards the Pcd option. But as Ard points out to me, it needs to use a FixedPcd (using FixedPcdGet()) - this can only ever have a buildtime resolution. Regards, Leif (technically on holiday, so no patch review until Monday) On Fri, Jun 30, 2017 at 11:35:26AM +0800, Jun Nie wrote: > Hi, > > I am trying to add support to different reg offset and bit offset in > PL011 UART. It seems impossible to add macro in platform.dsc to enable > undef/redef in the header file with "#ifdef ZX_PL011_FLAG". Is there > any proper way to control the reg/bit offset definition? Or we have to > adopt the Linux driver method with a structure to hold different > offset value and wrap register access function as below? If so, > another Pcd is needed to specify the offset structure index for the > platforms. > > > static u16 pl011_st_offsets[REG_ARRAY_SIZE] = { > [REG_DR] = UART01x_DR, > [REG_ST_DMAWM] = ST_UART011_DMAWM, > [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT, > ... > } > > static unsigned int pl011_read(const struct uart_amba_port *uap, > unsigned int reg) > { > void __iomem *addr = uap->port.membase + uap->reg_offset[reg]; > > return (uap->port.iotype == UPIO_MEM32) ? > readl_relaxed(addr) : readw_relaxed(addr); > } > > Jun