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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id y192sm18468822wmy.6.2017.07.04.08.38.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Jul 2017 08:38:46 -0700 (PDT) Date: Tue, 4 Jul 2017 16:38:44 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, jsd@semihalf.com, jinghua@marvell.com Message-ID: <20170704153844.GQ26676@bivouac.eciton.net> References: <1499174653-330-1-git-send-email-mw@semihalf.com> <1499174653-330-11-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1499174653-330-11-git-send-email-mw@semihalf.com> User-Agent: Mutt/1.5.23 (2014-03-12) Subject: Re: [platforms: PATCH 10/10] Platform/Marvell: ComPhyLib: Add support for SATA ports on CP110 slave X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 15:37:10 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jul 04, 2017 at 03:24:13PM +0200, Marcin Wojtas wrote: > From: Ard Biesheuvel > > Add support for PHY_TYPE_SATA2 and PHY_TYPE_SATA3, which map to the > SATA ports on the second CP110's AHCI controller. > > While at it, add a missing newline in the debug output to make it more > legible. Now now, one logical change per patch please. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Ard Biesheuvel > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 20 +++++++++++--------- > 1 file changed, 11 insertions(+), 9 deletions(-) > > diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c > index de35265..5180060 100755 > --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c > +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c > @@ -54,21 +54,23 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; > */ > COMPHY_MUX_DATA Cp110ComPhyMuxData[] = { > /* Lane 0 */ > - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4}}}, > + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4}, > + {COMPHY_TYPE_SATA3, 0x4}}}, > /* Lane 1 */ > - {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}}, > + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4}, > + {COMPHY_TYPE_SATA2, 0x4}}}, > /* Lane 2 */ > {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, {COMPHY_TYPE_RXAUI0, 0x1}, > - {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}}, > + {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}, {COMPHY_TYPE_SATA2, 0x4}}}, > /* Lane 3 */ > - {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2}, > - {COMPHY_TYPE_SATA1, 0x4}}}, > + {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2}, > + {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}}, > /* Lane 4 */ > - {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2}, > + {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2}, > {COMPHY_TYPE_SFI, 0x2}, {COMPHY_TYPE_SGMII1, 0x1}}}, > /* Lane 5 */ > - {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2}, > - {COMPHY_TYPE_SATA1, 0x4}}}, > + {5, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2}, > + {COMPHY_TYPE_SATA1, 0x4}, {COMPHY_TYPE_SATA3, 0x4}}}, > }; > > COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = { > @@ -1840,7 +1842,7 @@ ComPhyCp110Init ( > break; > } > if (EFI_ERROR(Status)) { > - DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x", Lane, Status)); > + DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x\n", Lane, Status)); Please drop this hunk. Submit it separately if you care enough. / Leif > PtrComPhyMap->Type = COMPHY_TYPE_UNCONNECTED; > } > } > -- > 2.7.4 >