From: Leif Lindholm <leif.lindholm@linaro.org>
To: Marcin Wojtas <mw@semihalf.com>
Cc: edk2-devel-01 <edk2-devel@lists.01.org>,
Ard Biesheuvel <ard.biesheuvel@linaro.org>,
semihalf-dabros-jan <jsd@semihalf.com>,
Hua Jing <jinghua@marvell.com>
Subject: Re: [platforms: PATCH 09/10] Platform/Marvell: ComPhyLib: Use COMPHY_ prefix in macros
Date: Tue, 4 Jul 2017 17:02:00 +0100 [thread overview]
Message-ID: <20170704160200.GS26676@bivouac.eciton.net> (raw)
In-Reply-To: <CAPv3WKdFnDbB0=oQ=jSaK7g1UJd6qPa0ii5RjEZMa9O8CnYJ-A@mail.gmail.com>
On Tue, Jul 04, 2017 at 05:55:58PM +0200, Marcin Wojtas wrote:
> Hi Leif,
>
> 2017-07-04 17:36 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> > On Tue, Jul 04, 2017 at 03:24:12PM +0200, Marcin Wojtas wrote:
> >> This patch renames macros for speed, type and polarity from
> >> 'PHY_' to 'COMPHY_', so that to avoid confusion with network
> >> PHY's definitions.
> >
> > Which will be called? NETPHY?
> > I always assumed COMPHY stood for communications PHY - what does it
> > actually stand for? I guess this is a strike for only using
> > abbreviations permitted by the coding style :)
> > (No, I won't make you change it).
> > However...
> >
>
> It stands for Communication PHY indeed - the change was requested by
> Marvell team. If you won't mind too much, I'll fix the style pointed
> below and resend.
That's fine, but I'd appreciate if you could just mention that in the
commit message aswell.
(Something like "from 'PHY_' to 'COMPHY_' (Communication PHY), so as
to avoid confusion with network PHY's definitions (NETPHY)".)
Why NETworking is not COMmunications is a question I'll reserve for
the next Marvell employee I meet :)
Regards,
Leif
> Thanks,
> Marcin
>
> >> Contributed-under: TianoCore Contribution Agreement 1.0
> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> ---
> >> Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c | 98 ++++++++++++------------
> >> Platform/Marvell/Library/ComPhyLib/ComPhyLib.c | 22 +++---
> >> Platform/Marvell/Library/ComPhyLib/ComPhyLib.h | 90 +++++++++++-----------
> >> Platform/Marvell/Library/ComPhyLib/ComPhyMux.c | 4 +-
> >> 4 files changed, 107 insertions(+), 107 deletions(-)
> >>
> >> diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c
> >> index 329bbe8..de35265 100755
> >> --- a/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c
> >> +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyCp110.c
> >> @@ -54,40 +54,40 @@ DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE;
> >> */
> >> COMPHY_MUX_DATA Cp110ComPhyMuxData[] = {
> >> /* Lane 0 */
> >> - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII1, 0x1}, {PHY_TYPE_SATA1, 0x4}}},
> >> + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII1, 0x1}, {COMPHY_TYPE_SATA1, 0x4}}},
> >
> > Every entry in this struct now get a line over 90 characters. I wasn't
> > complaining when they hit just over 80, but this is stretching it a
> > bit far. Please wrap a bit further.
> >
> >> /* Lane 1 */
> >> - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_SATA0, 0x4}}},
> >> + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}},
> >> /* Lane 2 */
> >> - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x1}, {PHY_TYPE_RXAUI0, 0x1},
> >> - {PHY_TYPE_SFI, 0x1}, {PHY_TYPE_SATA0, 0x4}}},
> >> + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x1}, {COMPHY_TYPE_RXAUI0, 0x1},
> >> + {COMPHY_TYPE_SFI, 0x1}, {COMPHY_TYPE_SATA0, 0x4}}},
> >
> > And while doing that, please ensure the wrapped information ends up
> > aligne with the element they form part of. In this instance:
> >
> > {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, ...
> > {COMPHY_TYPE_RXAUI0, 0x1},
> >
> >> /* Lane 3 */
> >> - {8, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_RXAUI1, 0x1}, {PHY_TYPE_SGMII1, 0x2},
> >> - {PHY_TYPE_SATA1, 0x4}}},
> >> + {8, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_RXAUI1, 0x1}, {COMPHY_TYPE_SGMII1, 0x2},
> >> + {COMPHY_TYPE_SATA1, 0x4}}},
> >> /* Lane 4 */
> >> - {7, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII0, 0x2}, {PHY_TYPE_RXAUI0, 0x2},
> >> - {PHY_TYPE_SFI, 0x2}, {PHY_TYPE_SGMII1, 0x1}}},
> >> + {7, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII0, 0x2}, {COMPHY_TYPE_RXAUI0, 0x2},
> >> + {COMPHY_TYPE_SFI, 0x2}, {COMPHY_TYPE_SGMII1, 0x1}}},
> >> /* Lane 5 */
> >> - {6, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_SGMII2, 0x1}, {PHY_TYPE_RXAUI1, 0x2},
> >> - {PHY_TYPE_SATA1, 0x4}}},
> >> + {6, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_SGMII2, 0x1}, {COMPHY_TYPE_RXAUI1, 0x2},
> >> + {COMPHY_TYPE_SATA1, 0x4}}},
> >> };
> >>
> >> COMPHY_MUX_DATA Cp110ComPhyPipeMuxData[] = {
> >> /* Lane 0 */
> >> - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE0, 0x4} } },
> >> + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE0, 0x4} } },
> >
> > Please get rid of the spurious whitespaces between } } (on lines you
> > modify anyway only).
> >
> >> /* Lane 1 */
> >> - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1},
> >> - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE0, 0x4} } },
> >> + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1},
> >> + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE0, 0x4} } },
> >
> > And please do this indentation change here too, on the lines you are
> > modifying anyway.
> >
> >> /* Lane 2 */
> >> - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST0, 0x1},
> >> - {PHY_TYPE_PCIE0, 0x4} } },
> >> + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST0, 0x1},
> >> + {COMPHY_TYPE_PCIE0, 0x4} } },
> >> /* Lane 3 */
> >> - {3, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1},
> >> - {PHY_TYPE_PCIE0, 0x4} } },
> >> + {3, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1},
> >> + {COMPHY_TYPE_PCIE0, 0x4} } },
> >> /* Lane 4 */
> >> - {4, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_USB3_HOST1, 0x1},
> >> - {PHY_TYPE_USB3_DEVICE, 0x2}, {PHY_TYPE_PCIE1, 0x4} } },
> >> + {4, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_USB3_HOST1, 0x1},
> >> + {COMPHY_TYPE_USB3_DEVICE, 0x2}, {COMPHY_TYPE_PCIE1, 0x4} } },
> >> /* Lane 5 */
> >> - {2, {{PHY_TYPE_UNCONNECTED, 0x0}, {PHY_TYPE_PCIE2, 0x4} } },
> >> + {2, {{COMPHY_TYPE_UNCONNECTED, 0x0}, {COMPHY_TYPE_PCIE2, 0x4} } },
> >> };
> >>
> >
> > /
> > Leif
> >
> >> STATIC
> >> @@ -1102,7 +1102,7 @@ ComPhySgmiiRFUConfiguration (
> >> Data = 0x0 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET;
> >> Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK;
> >> Mask |= SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK;
> >> - if (SgmiiSpeed == PHY_SPEED_1_25G) {
> >> + if (SgmiiSpeed == COMPHY_SPEED_1_25G) {
> >> Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET;
> >> Data |= 0x6 << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET;
> >> } else {
> >> @@ -1320,7 +1320,7 @@ ComPhySfiPhyConfiguration (
> >>
> >> /* Set reference clock */
> >> Mask = HPIPE_MISC_ICP_FORCE_MASK | HPIPE_MISC_REFCLK_SEL_MASK;
> >> - Data = (SfiSpeed == PHY_SPEED_5_15625G) ?
> >> + Data = (SfiSpeed == COMPHY_SPEED_5_15625G) ?
> >> (0x0 << HPIPE_MISC_ICP_FORCE_OFFSET) : (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET);
> >> MmioAndThenOr32 (HpipeAddr + HPIPE_MISC_REG, ~Mask, Data);
> >>
> >> @@ -1348,7 +1348,7 @@ ComPhySfiPhyConfiguration (
> >> MmioOr32 (HpipeAddr + HPIPE_PWR_CTR_DTL_REG, HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK);
> >>
> >> /* Transmitter/Receiver Speed Divider Force */
> >> - if (SfiSpeed == PHY_SPEED_5_15625G) {
> >> + if (SfiSpeed == COMPHY_SPEED_5_15625G) {
> >> Mask = HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK |
> >> HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK |
> >> HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK |
> >> @@ -1380,7 +1380,7 @@ ComPhySfiSetAnalogParameters (
> >> MmioOr32 (HpipeAddr + HPIPE_DFE_REG0, HPIPE_DFE_RES_FORCE_MASK);
> >>
> >> /* Generation 1 setting_0 */
> >> - if (SfiSpeed == PHY_SPEED_5_15625G) {
> >> + if (SfiSpeed == COMPHY_SPEED_5_15625G) {
> >> Mask = HPIPE_GX_SET0_TX_EMPH1_MASK;
> >> Data = 0x6 << HPIPE_GX_SET0_TX_EMPH1_OFFSET;
> >> } else {
> >> @@ -1414,7 +1414,7 @@ ComPhySfiSetAnalogParameters (
> >> MmioAnd32 (HpipeAddr + HPIPE_G1_SET5_REG, ~HPIPE_GX_SET5_ICP_MASK);
> >>
> >> /* Generation 1 setting 1 */
> >> - if (SfiSpeed == PHY_SPEED_5_15625G) {
> >> + if (SfiSpeed == COMPHY_SPEED_5_15625G) {
> >> Mask = HPIPE_GX_SET1_RX_SELMUPI_MASK | HPIPE_GX_SET1_RX_SELMUPP_MASK;
> >> Data = 0x1 | (0x1 << HPIPE_GX_SET1_RX_SELMUPP_OFFSET);
> >> } else {
> >> @@ -1447,7 +1447,7 @@ ComPhySfiSetAnalogParameters (
> >> /* Generation 1 setting 3 */
> >> MmioOr32 (HpipeAddr + HPIPE_G1_SET3_REG, HPIPE_GX_SET3_FBCK_SEL_MASK);
> >>
> >> - if (SfiSpeed == PHY_SPEED_5_15625G) {
> >> + if (SfiSpeed == COMPHY_SPEED_5_15625G) {
> >> /* Force FFE (Feed Forward Equalization) to 5G */
> >> Mask = HPIPE_GX_SET3_FFE_CAP_SEL_MASK |
> >> HPIPE_GX_SET3_FFE_RES_SEL_MASK |
> >> @@ -1760,9 +1760,9 @@ ComPhyMuxCp110 (
> >>
> >> /* Fix the Type after check the PHY and PIPE configuration */
> >> for (Lane = 0; Lane < ComPhyMaxCount; Lane++)
> >> - if ((ComPhyMapPipeData[Lane].Type == PHY_TYPE_UNCONNECTED) &&
> >> - (ComPhyMapPhyData[Lane].Type == PHY_TYPE_UNCONNECTED))
> >> - SerdesMap[Lane].Type = PHY_TYPE_UNCONNECTED;
> >> + if ((ComPhyMapPipeData[Lane].Type == COMPHY_TYPE_UNCONNECTED) &&
> >> + (ComPhyMapPhyData[Lane].Type == COMPHY_TYPE_UNCONNECTED))
> >> + SerdesMap[Lane].Type = COMPHY_TYPE_UNCONNECTED;
> >> }
> >>
> >> VOID
> >> @@ -1786,7 +1786,7 @@ ComPhyCp110Init (
> >>
> >> /* Check if the first 4 Lanes configured as By-4 */
> >> for (Lane = 0, PtrComPhyMap = SerdesMap; Lane < 4; Lane++, PtrComPhyMap++) {
> >> - if (PtrComPhyMap->Type != PHY_TYPE_PCIE0) {
> >> + if (PtrComPhyMap->Type != COMPHY_TYPE_PCIE0) {
> >> PcieBy4 = 0;
> >> break;
> >> }
> >> @@ -1797,39 +1797,39 @@ ComPhyCp110Init (
> >> DEBUG((DEBUG_INFO, "ComPhy: Initialize serdes number %d\n", Lane));
> >> DEBUG((DEBUG_INFO, "ComPhy: Serdes Type = 0x%x\n", PtrComPhyMap->Type));
> >> switch (PtrComPhyMap->Type) {
> >> - case PHY_TYPE_UNCONNECTED:
> >> + case COMPHY_TYPE_UNCONNECTED:
> >> continue;
> >> break;
> >> - case PHY_TYPE_PCIE0:
> >> - case PHY_TYPE_PCIE1:
> >> - case PHY_TYPE_PCIE2:
> >> - case PHY_TYPE_PCIE3:
> >> + case COMPHY_TYPE_PCIE0:
> >> + case COMPHY_TYPE_PCIE1:
> >> + case COMPHY_TYPE_PCIE2:
> >> + case COMPHY_TYPE_PCIE3:
> >> Status = ComPhyPciePowerUp(Lane, PcieBy4, HpipeBaseAddr, ComPhyBaseAddr);
> >> break;
> >> - case PHY_TYPE_SATA0:
> >> - case PHY_TYPE_SATA1:
> >> + case COMPHY_TYPE_SATA0:
> >> + case COMPHY_TYPE_SATA1:
> >> Status = ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, MVHW_CP0_AHCI0_ID);
> >> break;
> >> - case PHY_TYPE_SATA2:
> >> - case PHY_TYPE_SATA3:
> >> + case COMPHY_TYPE_SATA2:
> >> + case COMPHY_TYPE_SATA3:
> >> Status = ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, MVHW_CP1_AHCI0_ID);
> >> break;
> >> - case PHY_TYPE_USB3_HOST0:
> >> - case PHY_TYPE_USB3_HOST1:
> >> + case COMPHY_TYPE_USB3_HOST0:
> >> + case COMPHY_TYPE_USB3_HOST1:
> >> Status = ComphyUsb3PowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr);
> >> break;
> >> - case PHY_TYPE_SGMII0:
> >> - case PHY_TYPE_SGMII1:
> >> - case PHY_TYPE_SGMII2:
> >> - case PHY_TYPE_SGMII3:
> >> + case COMPHY_TYPE_SGMII0:
> >> + case COMPHY_TYPE_SGMII1:
> >> + case COMPHY_TYPE_SGMII2:
> >> + case COMPHY_TYPE_SGMII3:
> >> Status = ComPhySgmiiPowerUp(Lane, PtrComPhyMap->Speed, HpipeBaseAddr,
> >> ComPhyBaseAddr);
> >> break;
> >> - case PHY_TYPE_SFI:
> >> + case COMPHY_TYPE_SFI:
> >> Status = ComPhySfiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr, PtrComPhyMap->Speed);
> >> break;
> >> - case PHY_TYPE_RXAUI0:
> >> - case PHY_TYPE_RXAUI1:
> >> + case COMPHY_TYPE_RXAUI0:
> >> + case COMPHY_TYPE_RXAUI1:
> >> Status = ComPhyRxauiPowerUp(Lane, HpipeBaseAddr, ComPhyBaseAddr);
> >> break;
> >> default:
> >> @@ -1841,7 +1841,7 @@ ComPhyCp110Init (
> >> }
> >> if (EFI_ERROR(Status)) {
> >> DEBUG ((DEBUG_ERROR, "Failed to initialize Lane %d\n with Status = 0x%x", Lane, Status));
> >> - PtrComPhyMap->Type = PHY_TYPE_UNCONNECTED;
> >> + PtrComPhyMap->Type = COMPHY_TYPE_UNCONNECTED;
> >> }
> >> }
> >> }
> >> diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c
> >> index b61ccb6..3eb5d9f 100644
> >> --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c
> >> +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.c
> >> @@ -122,16 +122,16 @@ ParseSerdesTypeString (
> >> UINT32 i;
> >>
> >> if (String == NULL)
> >> - return PHY_TYPE_INVALID;
> >> + return COMPHY_TYPE_INVALID;
> >>
> >> - for (i = 0; i < PHY_TYPE_MAX; i++) {
> >> + for (i = 0; i < COMPHY_TYPE_MAX; i++) {
> >> if (StrCmp (String, TypeStringTable[i]) == 0) {
> >> return i;
> >> }
> >> }
> >>
> >> /* PCD string doesn't match any supported SerDes Type */
> >> - return PHY_TYPE_INVALID;
> >> + return COMPHY_TYPE_INVALID;
> >> }
> >>
> >> /* This function converts SerDes speed in MHz to enum with SerDesSpeed */
> >> @@ -144,14 +144,14 @@ ParseSerdesSpeed (
> >> UINT32 ValueTable [] = {0, 1250, 1500, 2500, 3000, 3125,
> >> 5000, 5156, 6000, 6250, 10310};
> >>
> >> - for (i = 0; i < PHY_SPEED_MAX; i++) {
> >> + for (i = 0; i < COMPHY_SPEED_MAX; i++) {
> >> if (Value == ValueTable[i]) {
> >> return i;
> >> }
> >> }
> >>
> >> /* PCD SerDes speed value doesn't match any supported SerDes speed */
> >> - return PHY_SPEED_INVALID;
> >> + return COMPHY_SPEED_INVALID;
> >> }
> >>
> >> CHAR16 *
> >> @@ -160,7 +160,7 @@ GetTypeString (
> >> )
> >> {
> >>
> >> - if (Type < 0 || Type > PHY_TYPE_MAX) {
> >> + if (Type < 0 || Type > COMPHY_TYPE_MAX) {
> >> return L"invalid";
> >> }
> >>
> >> @@ -295,13 +295,13 @@ MvComPhyInit (
> >> ParseSerdesSpeed (LaneData[Index].SpeedValue[Lane]);
> >> PtrChipCfg->MapData[Lane].Invert = (UINT32)LaneData[Index].InvFlag[Lane];
> >>
> >> - if ((PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_INVALID) ||
> >> - (PtrChipCfg->MapData[Lane].Speed == PHY_SPEED_ERROR) ||
> >> - (PtrChipCfg->MapData[Lane].Type == PHY_TYPE_INVALID)) {
> >> + if ((PtrChipCfg->MapData[Lane].Speed == COMPHY_SPEED_INVALID) ||
> >> + (PtrChipCfg->MapData[Lane].Speed == COMPHY_SPEED_ERROR) ||
> >> + (PtrChipCfg->MapData[Lane].Type == COMPHY_TYPE_INVALID)) {
> >> DEBUG((DEBUG_ERROR, "ComPhy: No valid phy speed or type for lane %d, "
> >> "setting lane as unconnected\n", Lane + 1));
> >> - PtrChipCfg->MapData[Lane].Type = PHY_TYPE_UNCONNECTED;
> >> - PtrChipCfg->MapData[Lane].Speed = PHY_SPEED_INVALID;
> >> + PtrChipCfg->MapData[Lane].Type = COMPHY_TYPE_UNCONNECTED;
> >> + PtrChipCfg->MapData[Lane].Speed = COMPHY_SPEED_INVALID;
> >> }
> >> };
> >>
> >> diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h
> >> index 3c589f2..3898978 100644
> >> --- a/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h
> >> +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyLib.h
> >> @@ -63,51 +63,51 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> >> }
> >>
> >> /***** ComPhy *****/
> >> -#define PHY_SPEED_ERROR 0
> >> -#define PHY_SPEED_1_25G 1
> >> -#define PHY_SPEED_1_5G 2
> >> -#define PHY_SPEED_2_5G 3
> >> -#define PHY_SPEED_3G 4
> >> -#define PHY_SPEED_3_125G 5
> >> -#define PHY_SPEED_5G 6
> >> -#define PHY_SPEED_5_15625G 7
> >> -#define PHY_SPEED_6G 8
> >> -#define PHY_SPEED_6_25G 9
> >> -#define PHY_SPEED_10_3125G 10
> >> -#define PHY_SPEED_MAX 11
> >> -#define PHY_SPEED_INVALID 0xff
> >> -
> >> -#define PHY_TYPE_UNCONNECTED 0
> >> -#define PHY_TYPE_PCIE0 1
> >> -#define PHY_TYPE_PCIE1 2
> >> -#define PHY_TYPE_PCIE2 3
> >> -#define PHY_TYPE_PCIE3 4
> >> -#define PHY_TYPE_SATA0 5
> >> -#define PHY_TYPE_SATA1 6
> >> -#define PHY_TYPE_SATA2 7
> >> -#define PHY_TYPE_SATA3 8
> >> -#define PHY_TYPE_SGMII0 9
> >> -#define PHY_TYPE_SGMII1 10
> >> -#define PHY_TYPE_SGMII2 11
> >> -#define PHY_TYPE_SGMII3 12
> >> -#define PHY_TYPE_QSGMII 13
> >> -#define PHY_TYPE_USB3_HOST0 14
> >> -#define PHY_TYPE_USB3_HOST1 15
> >> -#define PHY_TYPE_USB3_DEVICE 16
> >> -#define PHY_TYPE_XAUI0 17
> >> -#define PHY_TYPE_XAUI1 18
> >> -#define PHY_TYPE_XAUI2 19
> >> -#define PHY_TYPE_XAUI3 20
> >> -#define PHY_TYPE_RXAUI0 21
> >> -#define PHY_TYPE_RXAUI1 22
> >> -#define PHY_TYPE_SFI 23
> >> -#define PHY_TYPE_MAX 24
> >> -#define PHY_TYPE_INVALID 0xff
> >> -
> >> -#define PHY_POLARITY_NO_INVERT 0
> >> -#define PHY_POLARITY_TXD_INVERT 1
> >> -#define PHY_POLARITY_RXD_INVERT 2
> >> -#define PHY_POLARITY_ALL_INVERT (PHY_POLARITY_TXD_INVERT | PHY_POLARITY_RXD_INVERT)
> >> +#define COMPHY_SPEED_ERROR 0
> >> +#define COMPHY_SPEED_1_25G 1
> >> +#define COMPHY_SPEED_1_5G 2
> >> +#define COMPHY_SPEED_2_5G 3
> >> +#define COMPHY_SPEED_3G 4
> >> +#define COMPHY_SPEED_3_125G 5
> >> +#define COMPHY_SPEED_5G 6
> >> +#define COMPHY_SPEED_5_15625G 7
> >> +#define COMPHY_SPEED_6G 8
> >> +#define COMPHY_SPEED_6_25G 9
> >> +#define COMPHY_SPEED_10_3125G 10
> >> +#define COMPHY_SPEED_MAX 11
> >> +#define COMPHY_SPEED_INVALID 0xff
> >> +
> >> +#define COMPHY_TYPE_UNCONNECTED 0
> >> +#define COMPHY_TYPE_PCIE0 1
> >> +#define COMPHY_TYPE_PCIE1 2
> >> +#define COMPHY_TYPE_PCIE2 3
> >> +#define COMPHY_TYPE_PCIE3 4
> >> +#define COMPHY_TYPE_SATA0 5
> >> +#define COMPHY_TYPE_SATA1 6
> >> +#define COMPHY_TYPE_SATA2 7
> >> +#define COMPHY_TYPE_SATA3 8
> >> +#define COMPHY_TYPE_SGMII0 9
> >> +#define COMPHY_TYPE_SGMII1 10
> >> +#define COMPHY_TYPE_SGMII2 11
> >> +#define COMPHY_TYPE_SGMII3 12
> >> +#define COMPHY_TYPE_QSGMII 13
> >> +#define COMPHY_TYPE_USB3_HOST0 14
> >> +#define COMPHY_TYPE_USB3_HOST1 15
> >> +#define COMPHY_TYPE_USB3_DEVICE 16
> >> +#define COMPHY_TYPE_XAUI0 17
> >> +#define COMPHY_TYPE_XAUI1 18
> >> +#define COMPHY_TYPE_XAUI2 19
> >> +#define COMPHY_TYPE_XAUI3 20
> >> +#define COMPHY_TYPE_RXAUI0 21
> >> +#define COMPHY_TYPE_RXAUI1 22
> >> +#define COMPHY_TYPE_SFI 23
> >> +#define COMPHY_TYPE_MAX 24
> >> +#define COMPHY_TYPE_INVALID 0xff
> >> +
> >> +#define COMPHY_POLARITY_NO_INVERT 0
> >> +#define COMPHY_POLARITY_TXD_INVERT 1
> >> +#define COMPHY_POLARITY_RXD_INVERT 2
> >> +#define COMPHY_POLARITY_ALL_INVERT (COMPHY_POLARITY_TXD_INVERT | COMPHY_POLARITY_RXD_INVERT)
> >>
> >> /***** SerDes IP registers *****/
> >> #define SD_EXTERNAL_CONFIG0_REG 0
> >> diff --git a/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c b/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c
> >> index 595745b..6589fec 100644
> >> --- a/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c
> >> +++ b/Platform/Marvell/Library/ComPhyLib/ComPhyMux.c
> >> @@ -57,8 +57,8 @@ ComPhyMuxCheckConfig (
> >> DEBUG((DEBUG_INFO, "Lane number %d, had invalid Type %d\n", Lane,
> >> ComPhyMapData->Type));
> >> DEBUG((DEBUG_INFO, "Set Lane %d as Type %d\n", Lane,
> >> - PHY_TYPE_UNCONNECTED));
> >> - ComPhyMapData->Type = PHY_TYPE_UNCONNECTED;
> >> + COMPHY_TYPE_UNCONNECTED));
> >> + ComPhyMapData->Type = COMPHY_TYPE_UNCONNECTED;
> >> } else {
> >> DEBUG((DEBUG_INFO, "Lane number %d, has Type %d\n", Lane,
> >> ComPhyMapData->Type));
> >> --
> >> 2.7.4
> >>
next prev parent reply other threads:[~2017-07-04 16:00 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-04 13:24 [platforms: PATCH 00/10] Armada 7k ComPhy upgrade Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 01/10] Platform/Marvell: ComPhyLib: Cleanup and fix SerDes lanes assignment Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 02/10] Platform/Marvell: ComPhyLib: Rename KR to SFI Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 03/10] Platform/Marvell: Update SerDes types on A70x0 development board Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 04/10] Platform/Marvell: ComPhyLib: Mark failing lane as unconnected Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 05/10] Platform/Marvell: ComPhyLib: Configure analog parameters for SATA Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 06/10] Platform/Marvell: ComPhyLib: Configure analog parameters for PCIE Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 07/10] Platform/Marvell: ComPhyLib: Add missing SFI and RXAUI configuration Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 08/10] Platform/Marvell: ComPhyLib: Move devices description to MvHwDescLib Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 09/10] Platform/Marvell: ComPhyLib: Use COMPHY_ prefix in macros Marcin Wojtas
2017-07-04 15:36 ` Leif Lindholm
2017-07-04 15:55 ` Marcin Wojtas
2017-07-04 16:02 ` Leif Lindholm [this message]
2017-07-04 16:13 ` Marcin Wojtas
2017-07-04 13:24 ` [platforms: PATCH 10/10] Platform/Marvell: ComPhyLib: Add support for SATA ports on CP110 slave Marcin Wojtas
2017-07-04 15:38 ` Leif Lindholm
2017-07-04 16:02 ` Ard Biesheuvel
2017-07-04 15:41 ` [platforms: PATCH 00/10] Armada 7k ComPhy upgrade Leif Lindholm
2017-07-04 15:59 ` Marcin Wojtas
2017-07-04 16:04 ` Leif Lindholm
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