From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 1404D21CF3B78 for ; Tue, 4 Jul 2017 09:54:57 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 0E9E1C0587D4; Tue, 4 Jul 2017 16:56:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 0E9E1C0587D4 Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx08.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 0E9E1C0587D4 Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id 403ED5DC1B; Tue, 4 Jul 2017 16:56:34 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Jordan Justen Date: Tue, 4 Jul 2017 18:56:22 +0200 Message-Id: <20170704165629.13610-2-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.32]); Tue, 04 Jul 2017 16:56:35 +0000 (UTC) Subject: [PATCH v2 1/8] OvmfPkg: widen PcdQ35TsegMbytes to UINT16 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 16:54:57 -0000 Widen PcdQ35TsegMbytes to UINT16, in preparation for setting it dynamically to the QEMU-advertized extended TSEG size (which is 16-bits wide). Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/OvmfPkg.dec | 2 +- OvmfPkg/PlatformPei/MemDetect.c | 6 +++--- OvmfPkg/SmmAccess/SmmAccessPei.c | 6 +++--- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 5627be0bab0a..021ac2a77211 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -91,15 +91,15 @@ [PcdsFixedAtBuild] gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7 ## The following setting controls how many megabytes we configure as TSEG on # Q35, for SMRAM purposes. Permitted values are: 1, 2, 8. Other values cause # undefined behavior. # # This PCD is only consulted if PcdSmmSmramRequire is TRUE (see below). - gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT8|0x20 + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index af96a04d194a..78a8e0de346c 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -344,15 +344,15 @@ PublishPeiMemory ( UINT32 PeiMemoryCap; LowerMemorySize = GetSystemMemorySizeBelow4gb (); if (FeaturePcdGet (PcdSmmSmramRequire)) { // // TSEG is chipped from the end of low RAM // - LowerMemorySize -= FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + LowerMemorySize -= FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; } // // If S3 is supported, then the S3 permanent PEI memory is placed next, // downwards. Its size is primarily dictated by CpuMpPei. The formula below // is an approximation. // @@ -452,15 +452,15 @@ QemuInitializeRam ( // Create memory HOBs // AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; - TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize = FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize, TRUE); } else { AddMemoryRangeHob (BASE_1MB, LowerMemorySize); } @@ -601,15 +601,15 @@ InitializeRamRegions ( if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; // // Make sure the TSEG area that we reported as a reserved memory resource // cannot be used for reserved memory allocations. // - TsegSize = FixedPcdGet8 (PcdQ35TsegMbytes) * SIZE_1MB; + TsegSize = FixedPcdGet16 (PcdQ35TsegMbytes) * SIZE_1MB; BuildMemoryAllocationHob ( GetSystemMemorySizeBelow4gb() - TsegSize, TsegSize, EfiReservedMemoryType ); } } diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccessPei.c index a4ce610a4650..76790e330f65 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.c +++ b/OvmfPkg/SmmAccess/SmmAccessPei.c @@ -315,24 +315,24 @@ SmmAccessPeiEntryPoint ( PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM), TopOfLowRamMb << MCH_BGSM_MB_SHIFT); // // Set TSEG Memory Base. // PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB), - (TopOfLowRamMb - FixedPcdGet8 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHIFT); + (TopOfLowRamMb - FixedPcdGet16 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHIFT); // // Set TSEG size, and disable TSEG visibility outside of SMM. Note that the // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is // *restricted* to SMM. // EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK; - EsmramcVal |= FixedPcdGet8 (PcdQ35TsegMbytes) == 8 ? MCH_ESMRAMC_TSEG_8MB : - FixedPcdGet8 (PcdQ35TsegMbytes) == 2 ? MCH_ESMRAMC_TSEG_2MB : + EsmramcVal |= FixedPcdGet16 (PcdQ35TsegMbytes) == 8 ? MCH_ESMRAMC_TSEG_8MB : + FixedPcdGet16 (PcdQ35TsegMbytes) == 2 ? MCH_ESMRAMC_TSEG_2MB : MCH_ESMRAMC_TSEG_1MB; EsmramcVal |= MCH_ESMRAMC_T_EN; PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal); // // TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it. -- 2.13.1.3.g8be5a757fa67