From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4A1B021CF3B8A for ; Tue, 4 Jul 2017 09:54:59 -0700 (PDT) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 4677A4ACC7; Tue, 4 Jul 2017 16:56:37 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mx1.redhat.com 4677A4ACC7 Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; dmarc=none (p=none dis=none) header.from=redhat.com Authentication-Results: ext-mx09.extmail.prod.ext.phx2.redhat.com; spf=pass smtp.mailfrom=lersek@redhat.com DKIM-Filter: OpenDKIM Filter v2.11.0 mx1.redhat.com 4677A4ACC7 Received: from lacos-laptop-7.usersys.redhat.com (ovpn-116-126.phx2.redhat.com [10.3.116.126]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7F0F95DC1B; Tue, 4 Jul 2017 16:56:36 +0000 (UTC) From: Laszlo Ersek To: edk2-devel-01 Cc: Jordan Justen Date: Tue, 4 Jul 2017 18:56:24 +0200 Message-Id: <20170704165629.13610-4-lersek@redhat.com> In-Reply-To: <20170704165629.13610-1-lersek@redhat.com> References: <20170704165629.13610-1-lersek@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.38]); Tue, 04 Jul 2017 16:56:37 +0000 (UTC) Subject: [PATCH v2 3/8] OvmfPkg/SmmAccess: prepare for PcdQ35TsegMbytes becoming dynamic X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 04 Jul 2017 16:54:59 -0000 In one of the next patches we'll turn PcdQ35TsegMbytes into a dynamic PCD, to be set by PlatformPei. Jordan suggested to use gEfiPeiMemoryDiscoveredPpiGuid as SmmAccessPei's DEPEX for making sure that PlatformPei sets the PCD before SmmAccessPei consumes it. (PlatformPei installs the permanent PEI RAM.) Such a DEPEX is supposed to mirror physical firmware, where anything related to SMRAM cannot run before said platform's physical RAM is discovered (signaled by the presence of gEfiPeiMemoryDiscoveredPpiGuid). Introduce the FetchQ35TsegMbytes() function and the "mQ35TsegMbytes" extern variable to "SmramInternal.h" and "SmramInternal.c": - Both SmmAccess modules (PEIM and DXE driver) are supposed to call FetchQ35TsegMbytes() in their respective entry point functions, saving PcdQ35TsegMbytes into "mQ35TsegMbytes". This way dynamic PCD fetches can be kept out of PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions later (when we add support for extended TSEG size). - We can thus replace the current PcdQ35TsegMbytes fetches in SmmAccessPei's entry point function as well, with reads from "mQ35TsegMbytes". Cc: Jordan Justen Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- OvmfPkg/SmmAccess/SmmAccess2Dxe.inf | 3 +++ OvmfPkg/SmmAccess/SmmAccessPei.inf | 4 ++-- OvmfPkg/SmmAccess/SmramInternal.h | 13 +++++++++++++ OvmfPkg/SmmAccess/SmmAccess2Dxe.c | 1 + OvmfPkg/SmmAccess/SmmAccessPei.c | 7 ++++--- OvmfPkg/SmmAccess/SmramInternal.c | 17 +++++++++++++++++ 6 files changed, 40 insertions(+), 5 deletions(-) diff --git a/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf b/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf index 31e4dfa02991..1bc88fa050c7 100644 --- a/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf +++ b/OvmfPkg/SmmAccess/SmmAccess2Dxe.inf @@ -50,9 +50,12 @@ [LibraryClasses] [Protocols] gEfiSmmAccess2ProtocolGuid ## PRODUCES [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes + [Depex] TRUE diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.inf b/OvmfPkg/SmmAccess/SmmAccessPei.inf index 3908b085da3a..09f3b63446df 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.inf +++ b/OvmfPkg/SmmAccess/SmmAccessPei.inf @@ -55,15 +55,15 @@ [LibraryClasses] PciLib PeiServicesLib PeimEntryPoint [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire -[FixedPcd] +[Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes [Ppis] gPeiSmmAccessPpiGuid ## PRODUCES [Depex] - TRUE + gEfiPeiMemoryDiscoveredPpiGuid diff --git a/OvmfPkg/SmmAccess/SmramInternal.h b/OvmfPkg/SmmAccess/SmramInternal.h index 4e9ac05fad1c..c9c9a7a59d4b 100644 --- a/OvmfPkg/SmmAccess/SmramInternal.h +++ b/OvmfPkg/SmmAccess/SmramInternal.h @@ -27,14 +27,27 @@ // typedef enum { DescIdxSmmS3ResumeState = 0, DescIdxMain = 1, DescIdxCount = 2 } DESCRIPTOR_INDEX; +// +// The value of PcdQ35TsegMbytes is saved into this variable at module startup. +// +extern UINT16 mQ35TsegMbytes; + +/** + Save PcdQ35TsegMbytes into mQ35TsegMbytes. +**/ +VOID +FetchQ35TsegMbytes ( + VOID + ); + /** Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL object, from the D_LCK and T_EN bits. PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rely on the LockState and OpenState fields being up-to-date on entry, and they need diff --git a/OvmfPkg/SmmAccess/SmmAccess2Dxe.c b/OvmfPkg/SmmAccess/SmmAccess2Dxe.c index d5130399b030..eaaf96e7e94b 100644 --- a/OvmfPkg/SmmAccess/SmmAccess2Dxe.c +++ b/OvmfPkg/SmmAccess/SmmAccess2Dxe.c @@ -145,12 +145,13 @@ SmmAccess2DxeEntryPoint ( ) { // // This module should only be included if SMRAM support is required. // ASSERT (FeaturePcdGet (PcdSmmSmramRequire)); + FetchQ35TsegMbytes (); GetStates (&mAccess2.LockState, &mAccess2.OpenState); return gBS->InstallMultipleProtocolInterfaces (&ImageHandle, &gEfiSmmAccess2ProtocolGuid, &mAccess2, NULL); } diff --git a/OvmfPkg/SmmAccess/SmmAccessPei.c b/OvmfPkg/SmmAccess/SmmAccessPei.c index 76790e330f65..aba3aeb9f4bd 100644 --- a/OvmfPkg/SmmAccess/SmmAccessPei.c +++ b/OvmfPkg/SmmAccess/SmmAccessPei.c @@ -314,25 +314,26 @@ SmmAccessPeiEntryPoint ( TopOfLowRamMb << MCH_GBSM_MB_SHIFT); PciWrite32 (DRAMC_REGISTER_Q35 (MCH_BGSM), TopOfLowRamMb << MCH_BGSM_MB_SHIFT); // // Set TSEG Memory Base. // + FetchQ35TsegMbytes (); PciWrite32 (DRAMC_REGISTER_Q35 (MCH_TSEGMB), - (TopOfLowRamMb - FixedPcdGet16 (PcdQ35TsegMbytes)) << MCH_TSEGMB_MB_SHIFT); + (TopOfLowRamMb - mQ35TsegMbytes) << MCH_TSEGMB_MB_SHIFT); // // Set TSEG size, and disable TSEG visibility outside of SMM. Note that the // T_EN bit has inverse meaning; when T_EN is set, then TSEG visibility is // *restricted* to SMM. // EsmramcVal &= ~(UINT32)MCH_ESMRAMC_TSEG_MASK; - EsmramcVal |= FixedPcdGet16 (PcdQ35TsegMbytes) == 8 ? MCH_ESMRAMC_TSEG_8MB : - FixedPcdGet16 (PcdQ35TsegMbytes) == 2 ? MCH_ESMRAMC_TSEG_2MB : + EsmramcVal |= mQ35TsegMbytes == 8 ? MCH_ESMRAMC_TSEG_8MB : + mQ35TsegMbytes == 2 ? MCH_ESMRAMC_TSEG_2MB : MCH_ESMRAMC_TSEG_1MB; EsmramcVal |= MCH_ESMRAMC_T_EN; PciWrite8 (DRAMC_REGISTER_Q35 (MCH_ESMRAMC), EsmramcVal); // // TSEG should be closed (see above), but unlocked, initially. Set G_SMRAME // (Global SMRAM Enable) too, as both D_LCK and T_EN depend on it. diff --git a/OvmfPkg/SmmAccess/SmramInternal.c b/OvmfPkg/SmmAccess/SmramInternal.c index c3267ca94031..ae1e9069aca6 100644 --- a/OvmfPkg/SmmAccess/SmramInternal.c +++ b/OvmfPkg/SmmAccess/SmramInternal.c @@ -13,18 +13,35 @@ WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. **/ #include #include #include +#include #include #include "SmramInternal.h" +// +// The value of PcdQ35TsegMbytes is saved into this variable at module startup. +// +UINT16 mQ35TsegMbytes; + +/** + Save PcdQ35TsegMbytes into mQ35TsegMbytes. +**/ +VOID +FetchQ35TsegMbytes ( + VOID + ) +{ + mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes); +} + /** Read the MCH_SMRAM and ESMRAMC registers, and update the LockState and OpenState fields in the PEI_SMM_ACCESS_PPI / EFI_SMM_ACCESS2_PROTOCOL object, from the D_LCK and T_EN bits. PEI_SMM_ACCESS_PPI and EFI_SMM_ACCESS2_PROTOCOL member functions can rely on the LockState and OpenState fields being up-to-date on entry, and they need -- 2.13.1.3.g8be5a757fa67